Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device

ABSTRACT

In order to fabricate a high performance thin film semiconductor device using a low temperature process in which it is possible to use low price glass substrates, a thin film semiconductor device has been fabricated by forming a silicon film at less than 450° C., and, after crystallization, keeping the maximum processing temperature at or below 350° C. 
     In applying the present invention to the fabrication of an active matrix liquid crystal display, it is possible to both easily and reliably fabricate a large, high-quality liquid crystal display. Additionally, in applying the present invention to the fabrication of other electronic circuits as well, it is possible to both easily and reliably fabricate high-quality electronic circuits.

FIELD OF TECHNOLOGY

The present invention is related to the fabrication method for a thinfilm semiconductor device, the thin film semiconductor device itself,liquid crystal displays, and electronic devices applicable to activematrix liquid crystal displays and the like.

BACKGROUND TECHNOLOGY

In recent years, along with increases in screen size and improvements inresolution, the driving methods for liquid crystal displays (LCDs) aremoving from simple matrix methods to active matrix methods; and thedisplays are becoming capable of displaying large amounts ofinformation. LCDs with more than several hundreds of thousands pixelsare possible with active matrix methods which place a switchingtransistor at each pixel. Transparent insulating substrates such asfused quartz and glass which allow the fabrication of transparentdisplays are used as substrates for all types of LCDs. Althoughordinarily semiconductor layers such as amorphous silicon orpolycrystalline silicon are used as the active layer in thin filmtransistors (TFTs), the use of polycrystalline silicon which has higheroperating speeds is advantageous for the case of producing monolithicdisplays which include integrated driving circuits. When polycrystallinesilicon is used as the active layer, fused quartz is used as thesubstrate; and a so-called "high temperature" process in which themaximum processing temperature exceeds 1000° C. is used to fabricate theTFTs. On the other hand, for the case of an amorphous silicon activelayer, a common glass substrate can be used. For increases in LCDdisplay size while maintaining low costs, such use of low-cost commonglass substrates is indispensable. Such amorphous silicon layers,however, have such problems as electrical characteristics far inferiorto those of polysilicon layers and slow operating speed. Since the hightemperature process polysilicon TFTs use quartz substrates, however,there are problems with increasing display size and decreasing costs.Consequently, there is a strong need for technology which can fabricatea thin film semiconductor device employing a semiconductor layer such aspolycrystalline silicon as the active layer upon a common glasssubstrate. But, when using large substrates which are well-suited tomass production, there is a severe restriction in that the substratesmust be kept below a maximum processing temperature of about 570° C. inorder to avoid deformation of the substrates. In other words, technologywhich can produce, under such restrictions, the active layer of thinfilm transistors capable of controlling a liquid crystal display and ofthin film transistors which can operate driving circuits at high speedis desired. These devices are currently known as the present lowtemperature poly-Si TFTs.

Previous low temperature poly-Si TFTs are shown on p. 387 of the SID(Society for Information Display) '93 Digest (1993). According to thisdescription, 50 nm of amorphous silicon (a-Si) is first deposited at550° C. by LPCVD using monosilane (SiH₄) as the source gas and thenconverted from a-Si to poly-Si by laser irradiation. After patterning ofthe poly-Si layer, a gate insulator layer of SiO₂ is deposited byECR-PECVD at a substrate temperature of 100° C. Following formation ofthe tantalum (Ta) gate electrode on top of the gate insulator layer,self-aligned transistor source and drain regions are formed in thesilicon layer by ion implantation of donor or acceptor impurities whileusing the gate electrode as a mask. This ion implantation, known as "iondoping", is accomplished by a non-mass separating ion implanter.Hydrogen-diluted phosphine (PH₃), diborane (B₂ H₆) or similar gas isused as a source gas for ion doping. Activation of the impurities iscarried out at 300° C. Following deposition of an interlevel insulatorlayer, electrodes and interconnects such as indium tin oxide (ITO) andaluminum (Al) are deposited to complete the thin film semiconductordevice.

As described below, however, there are several inherent problems withpoly-Si TFTs fabricated by the existing technology in the lowtemperature process which act as impediments to the adoption of thistechnology into mass production.

1. The high processing temperature of 550° C. prevents the use oflow-priced glass leading to a steep rise in product prices.Additionally, the degree of warp of the glass substrates as a result oftheir own weight increases as substrate size increases, and increases inliquid crystal display (LCD) sizes are not possible.

2. The appropriate irradiation conditions necessary to obtain uniformlaser irradiation over the entire substrate are severe and fall within anarrow range. As a result, the crystallization of the film can vary fromuniform to non-uniform from lot to lot and reliable production is notpossible.

3. During the ion doping or subsequent low temperature activation at300°-350° C. of the source and drain regions which are self-aligned withrespect to the gate electrode, the problem of unsuccessful activationoccasionally occurs. In other words, the resistance of the source anddrain regions is several gigaohms. Especially when producing TFTs withlightly doped drains (LDD), this problem is serious and is a cause ofsignificant decreases in production yield.

4. Although only SiO₂ formed by ECR-PECVD yields suitable transistorproperties in low temperature process poly-Si TFTs, it is difficult toincrease the size of the ECR source in the ECR-PECVD equipment therebymaking ECR-PECVD unsuitable for large LCD panels. Furthermore, thethroughput is extremely poor. Consequently, ECR-PECVD reactors are notsuitable as mass production-compatible, practical gate oxide filmdeposition equipment applicable to the manufacture of large sizedisplays.

5. Use of means such as laser irradiation for melt crystallization ofsemiconductor films like silicon results in partial agglomeration whichcan lead to large variations in the electrical properties of thesemiconductor layer, roughness of the semiconductor layer, and decreasesin the gate-source or gate-drain electrical breakdown strength.

6. When low cost, conventional glass substrates were used, theunderlevel protection layer necessary to effectively prevent penetrationof impurities from the glass into the semiconductor layer was not theunderlevel protection layer of the semiconductor devices which showedthe optimum electrical properties. In other words, making the underlevelprotection layer thicker to prevent impurity penetration leads to thedeterioration of the electrical properties of the semiconductor devicefrom stress generated by the underlayer or generates cracks in thesemiconductor device.

7. When plasma enhanced chemical vapor deposition (PECVD) is used toproduce the semiconductor films, elements such as fluorine (F) andcarbon (C), constitutive elements of vapors used in cleaning thedeposition chamber which may remain after cleaning, may be incorporatedas impurities into the films. The result is that the amount ofimpurities incorporated into the substrates varies, and it is notpossible to reliably produce excellent thin film semiconductor devices.

8. As the deposition temperature for semiconductor films in low pressurechemical vapor deposition (LPVCD) decreases, compatibility betweenuniformity within a substrate and the deposition rate is difficult. Inother words, because the deposition rate decreases when the depositiontemperature is lowered, the increase in pressure necessary to compensatefor this behavior results in significant worsening of the uniformityover a single substrate. This tendency becomes noticeably morepronounced as the substrate size becomes larger and is a major obstacleto the mass production of large LCDs.

9. There are three types of non-uniformity of the electricalcharacteristics of thin film semiconductor devices. In addition tovariations within a single substrate, there are also variations fromsubstrate to substrate in a single lot as well as variations betweendifferent lots. In the thin film semiconductor devices and thefabrication procedures of the existing technology, it is not possible tocontrol these three types of non-uniformity. In particular, there hasbeen almost no thought given to the variation in properties seen fromlot to lot.

10. In the fabrication of semiconductor thin films by PECVD, theadhesion between the semiconductor layer and the protective underlayeris poor; and numerous crater-shaped holes are generated in thesemiconductor layer which can lead to delamination of the film in theworst case.

The present invention aims to solve the problems noted above with thepurpose of providing a means for reliably producing good thin filmsemiconductor devices through a realistically convenient method using aprocessing temperature which will allow the use of common large glasssubstrates.

DESCRIPTION OF THE INVENTION

The fundamental principles and operation of the present invention willbe explained with reference to the drawings.

FIGS. 1A-1D are cross-sectional schematic representations of thefabrication process for thin film semiconductor devices constituting anMIS field effect transistor. After giving an outline of the lowtemperature poly-Si TFT fabrication process using these figures, thedetails of the present invention will be explained for each processingstep.

(1, Outline of the Fabrication Procedure of a Thin Film SemiconductorDevice of the Present Invention)

In the present invention, a conventional non-alkaline glass is used asan example for substrate 101. First, an insulating underlevel protectionlayer 102 is formed on top of substrate 101 by a technique such asatmospheric pressure chemical vapor deposition (APCVD), PECVD, orsputtering. Next, a semiconductor layer such as intrinsic silicon, whichwill later become the active layer of the semiconductor device, isdeposited. The semiconductor layer can be formed by chemical vapordeposition (CVD) such as LPCVD, PECVD, or APCVD or by physical vapordeposition (PVD) such as sputtering or evaporation. Crystallization ofthe semiconductor layer so fabricated is achieved by short -timeirradiation using electromagnetic energy or optical energy such as fromlaser light. When the originally deposited semiconductor layer isamorphous or a mixture of amorphous and microcrystalline material, thisprocess is known as crystallization. On the other hand, if theoriginally deposited semiconductor layer is polycrystalline, the processis known as recrystallization. In this description of the presentinvention, both are simply referred to as "crystallization" unless it isnecessary to make a distinction. If the intensity of the energy fromlaser light or other source is high, the semiconductor layer willcrystallize by initially melting and then solidifying upon cooling. Thisis known as melt crystallization in the present invention. Conversely,crystallization in which the semiconductor layer does not melt butproceeds in the solid state is known as solid phase crystallization(SPC). Solid phase crystallization can be divided mainly into threetypes: furnace-SPC in which crystallization occurs at temperatures from550° C. to 650° C. for times ranging from a few hours to several tens ofhours, rapid thermal annealing (RTA) in which crystallization occurs ina very short time frame ranging from less than one second up to aboutone minute at temperatures of 700° to 1000° C., and very short time-SPC(VST-SPC) using low intensity energy such as from a laser. Although allthree types are suitable for use in the present invention, meltcrystallization, RTA and VST-SPC are particularly appropriate whenconsidered in light of processing which allows high productivity forlarge substrates. The reason for this is not only that thesecrystallization methods use extremely short irradiation periods but alsothat the whole substrate is not heated during crystallization of thesemiconductor layer since the irradiated area is localized with respectto the entire substrate area; and, therefore, no heat-induceddeformation or cracking of the substrate occurs. Followingcrystallization, the semiconductor layer is patterned; and then theactive semiconductor layer 103 is produced. See FIG. 1A.

After formation of the semiconductor layer, the gate insulator layer 104is formed by a method such as CVD or PVD. Several methods can beconsidered for the fabrication of insulating films, but a fabricationtemperature of 350° C. or less is desirable. This is essential to avoidthermal degradation of the MOS interface and the insulating film. Thisis applicable to subsequent steps in the fabrication process as well.Processing temperatures following fabrication of the gate insulatorlayer must be kept at or below 350° C. Doing so allows high performancesemiconductor devices to be produced both easily and reliably.

Next, a thin film which will become the gate electrode 105 is depositedby a method such as PVD or CVD. Since the same material is usually usedfor both the gate electrode and the gate interconnects and both arefabricated in the same step, it is desirable to use a material which haslow electrical resistance and is stable with respect to thermalprocessing around 350° C. After patterning of the thin film for the gateelectrode, ion incorporation 106 into the semiconductor layer isemployed to form the source and drain regions 107 and the channel region108. See FIG. 1C. During this process, the gate electrode acts as a maskfor ion implantation so that the channel is formed only underneath thegate in a self-aligned structure. For impurity ion incorporation, bothion doping, in which non-mass separation equipment is used andhydrogenated impurity species as well as hydrogen are incorporated intothe film, and ion implantation, in which mass-separation ion implantersare used and only the desired impurities themselves are incorporatedinto the film, are applicable. Source gases for ion doping usehydrogenated species of the impurity ions such as phosphine (PH₃) anddiborane (B₂ H₆) which are diluted in hydrogen to concentrations of 0.1%to 10%. In the case of ion implantation, hydrogen ions (protons ormolecular hydrogen ions) are implanted following the implantation of thedesired impurity elements by themselves. In order to maintain a stableMOS interface and gate insulator layer, the temperature must be kept ator below 350° C. for both ion doping and ion implantation. In order toalways reliably carry out the impurity activation at a low temperatureof 350° C. or less, it is desirable to keep the substrate temperatureabove 200° C. during implantation. On the other hand, to ensure a lowtemperature activation of impurity ions implanted in the channel tocontrol the transistor threshold voltage or impurity ions implanted inlightly doped regions such as those used to form an LDD structure, it isnecessary to keep the substrate temperature at or above 250° C. duringion implantation. The result is that amorphization of the ion implantedregion can be avoided by performing the ion implantation at a such ahigh substrate temperature since recrystallization occurs simultaneouslywith damage to the semiconductor layer. In other words, the ionimplanted region remains crystalline following implantation, and thesubsequent activation of the implanted ions can still be achieved usinga low activation annealing temperature of less than about 350° C. Whenfabricating a CMOS TFT, the NMOS or PMOS region is alternately coveredby a suitable mask material such as polyimide resin, and ionimplantation is performed using the procedure above. If the substratetemperature is kept below approximately 300° C. during ion implantation,it is possible to use a cheap, easily preserved conventional photoresistas an ion implantation mask instead of the polyimide.

Next, the interlevel insulator film 109 is formed by either CVD or PVD.Following ion implantation and interlevel insulator film formation, ionactivation and interlevel insulator film densification are carried outby thermal annealing in a suitable thermal environment at temperaturesless than about 350° C. for a time ranging from several tens of minutesto a few hours. It is desirable for this annealing temperature to begreater than approximately 250° C. to ensure activation of the implantedions. Additionally, for effective densification of the interlevelinsulator film, a temperature of 300° C. or higher is preferred. Thefilm quality of the gate insulator layer and the interlevel insulatorlayer are normally different. Accordingly, during the opening of contactholes in the two insulator films following interlevel insulator filmformation, it is common for the etching rates in the two films to bedifferent. Under such conditions, an inverse taper in which the bottomof the contact hole is wider than the top or the formation of a canopycan result. During electrode formation, these undesirable structures canbe causes of poor contact between the electrode and underlying layers inthe device leading to so-called "contact failure." The generation ofcontact failure can be minimized by effective densification of theinterlevel insulator film. Following formation of the interlevelinsulator layer, contact holes are opened above the source and drainregions; and source and drain electrodes 110 and interconnects areformed by PVD or CVD to complete the fabrication of the thin filmsemiconductor device. See FIG. 1D.

(2, Detailed Explanations of the Individual Steps in the FabricationProcess of the Thin Film Semiconductor Device of the Present Invention)

(2-1, Substrates and Underlevel Protection Layers Suitable for thePresent Invention)

First, substrates and underlevel protection layers suitable for thepresent invention will be explained. For the present invention,substrates including conductive materials such as metals; ceramicmaterials such as silicon carbide (SiC), alumina (Al₂ O₃), and aluminumnitride (AlN); transparent insulating materials such as fused quartz andglass; semiconductor substrates such as silicon wafers or processed LSI;and crystalline insulators such as sapphire (trigonal Al₂ O₃) can beused. Low priced conventional glass substrates which can be used includeCorning Japan's 7059 and 1737 glasses, Nippon Electric Glass Co., Ltd.'sOA-2 glass, and NH Techno Glass's NA35. The type of substrate isimmaterial for the semiconductor film; and, as long as least part of thesubstrate surface is composed of an insulating material, thesemiconductor layer can be deposited on top of the insulating material.This insulating material is known as the underlevel protection layer inthe present invention disclosure. For example, if a fused quartzsubstrate is used as a substrate, it is acceptable to deposit asemiconductor film directly on top of the fused quartz substrate sincethe substrate itself is insulating. Or, it is acceptable to deposit thesemiconductor film on top of an underlevel protection layer such assilicon oxide (SiO_(x) : 0<x≦2) or silicon nitride (Si₃ N_(x) : 0<x≦4)which has been formed on top of the quartz substrate. When using anordinary glass substrate, it is possible to deposit the semiconductorfilm directly on top of the insulating glass, but it is desirable todeposit the semiconductor film after the formation of an insulatingunderlevel protection layer such as silicon oxide or silicon nitride toavoid penetration of mobile ions like sodium (Na), which are containedin the glass substrate, into the semiconductor film. By so doing, theoperational properties of the semiconductor device do not vary underoperation over a long time period or under high voltages, and thestability is increased. In the present invention, this stability iscalled transistor reliability. With the exception of using crystallineinsulating materials such as sapphire as substrates, it is desirable todeposit the semiconductor film on top of an underlevel protection layer.When using any type of ceramics as a substrate, the underlevelprotection layer serves to prevent sintering aids added to the ceramicsfrom diffusing into the semiconductor regions. In the case of metallicsubstrates, the use of an underlevel protection layer is essential tomaintain the insulating properties. Further, with semiconductorsubstrates or LSI elements, interlevel insulator films betweentransistors or between interconnects serve the role of underlevelprotection layers. The substrate size and shape adds no additionalrestrictions as long as the substrates do not shrink or distort in thethermal environment during processing. Substrates can be anywhere on theorder of 3 inch diameter (76.2 mm) disks to 560 mm×720 mm rectangularplates.

After the substrate has been cleaned in deionized water, an underlevelprotection layer of an oxide such as silicon oxide, aluminum oxide, ortantalum oxide; or a nitride such as silicon nitride is formed on thesubstrate by CVD methods such as APCVD, LPCVD, or PECVD; or by PVDmethods. Oxides and nitrides can be formed by initially forming ametallic layer such as silicon, aluminum, or tantalum on the substrateand then using a thermochemical or electrochemical reaction. Forexample, it is possible to form an approximately 200 nm thermal tantalumoxide film by first sputtering about 100 nm of tantalum and then heatingin an oxidizing atmosphere at about 450° C. to achieve thermaloxidation. Using APCVD, it is possible to deposit a silicon oxide filmusing monosilane (SiH₄) and oxygen as source gases at a substratetemperature of about 250° to 450° C. PECVD and sputtering can formunderlevel protection layers using substrate temperatures between roomtemperature and approximately 400° C.

In the present invention, because the semiconductor layer formed on topof the underlevel protection layer functions as the active layer for thetransistor and this semiconductor layer is formed by crystallization,the properties of the underlevel protection layer have a stronginfluence on the quality of the semiconductor layer. First, it isdesirable to have the center line mean surface roughness of theunderlevel protection layer be 3.0 nm or less. When a semiconductor filmsuch as silicon is deposited by CVD on top of an underlevel protectionlayer, the very first stage in film formation is the generation of manynuclei on top of the substrate. While these nuclei gradually grow, newnuclei form at sites on the underlevel protection layer which are notyet populated by nuclei. All of these nuclei grow, impinge on eachother, and eventually link to form a film. Regardless of whether thefilm is amorphous or crystalline, all deposited films, having theirorigin in such growth mechanisms, are constructed from regionscorresponding to nuclei in the early stages of growth. Consequently, ifthe nuclei density is low, the regions constituting the film will becomelarge. If the regions in the semiconductor film prior to crystallizationare large, the grains constituting the crystallized film will also belarge. When the grains in the semiconductor film are large, theelectrical properties, such as mobility, of the semiconductor devicehaving an active layer comprised of these grains improve. According tothe experiments of the inventor, it has become clear that the nucleidensity can be kept low if the center line mean surface roughness isabout 3.0 nm or less with the result being the ability to fabricate highperformance semiconductor devices. The reason for this seems to be thatthe irregularity in the surface of the underlevel protection layer isone factor in nucleation, and the nucleation density increases as thesurface irregularity becomes more pronounced. Further, it is desirableto have the center line mean surface roughness of the underlevelprotection layer be about 1.5 nm or less when the semiconductor layer ismelt crystallized. If the surface is this smooth, the meltedsemiconductor material such as silicon spreads readily over theunderlevel protection layer. Because of this, large diameter grains cangrow easily; and the properties of the thin film semiconductor deviceare improved dramatically. At the same time, local agglomeration of themolten material during solidification of the melted semiconductormaterial does not occur; and the uniformity within the molten regionincreases. The LSI scaling law applies to thin film semiconductordevices as well; and it appears that the miniaturization of elementswill continue in step with future integration. As transistor sizescontinue to shrink from the 1 μm order to submicron order, how to avoidlocal agglomeration will be an important issue. When fabricating thesemiconductor layer by melt crystallization, the center line meansurface roughness of the underlevel protection layer is ideally 1.0 nmor less. By meeting this criterion, it is possible to produce uniformfilms, without local agglomeration, from semiconductor films withlarge-diameter grains.

Another role of the underlevel protection layer is to prevent thediffusion of impurity elements from the substrate. To do so, it iseffective to combine at least two or more different types of films in alayered structure to act as the underlevel protection layer. Forexample, a layered structure comprising, from the substrate, a tantalumoxide film, a silicon nitride film, and a silicon oxide film can beused. There are various types of impurity elements in normal substrates,and these elements have different diffusion coefficients in thedifferent insulators mentioned above. It is easily possible to have acertain impurity element which diffuses slowly through one of the layerscomprising the underlevel protection layer but diffuses quickly throughanother layer. There are various impurity elements contained withinsubstrates; and, since there is a fixed underlevel protection layerthickness as will be explained later, underlevel protection layersformed by layering of different layers are more effective in preventingthe diffusion of impurities than single layers. Many different materialscan be considered for the underlevel protection layer; but, from theviewpoint of ease of fabrication by processes such as CVD, compositelayers of silicon nitride and silicon oxide are the most appropriate. Insuch two-layer composite or multilayer composite underlevel protectionlayers, it is desirable to have the upper most layer be of siliconoxide. This is because the interface states which are inevitablygenerated between the underlevel protection layer and the semiconductorlayer are minimized using silicon oxide. Especially for thinsemiconductor films less than a few hundred nm in which the depletionlayer formed under the transistor operating conditions can consume theentire semiconductor layer thickness, it is essential to suppress suchinterface states. In the present invention, the optimum semiconductorfilm thickness for the thin film semiconductor device varies slightlydepending on the fabrication process but is less than approximately 150nm. Nevertheless, because the quality of the semiconductor film is high,there are few grain boundary trapping states and few intragranulardefects. On account of this, the depletion layer extends completelythrough the semiconductor film when the transistor is in operation. Ifthere are many interface states generated at the interface between theunderlevel protection layer and the semiconductor layer, the spread ofthe depletion layer during channel formation is delayed, leading to ahigh threshold voltage since the interface states effectively act thesame as donor and acceptor ions. In other words, these interface statescan become one factor in the degradation of transistor properties. Theeffect of the surface of the underlevel protection layer on transistorproperties appears when the semiconductor layer is less thanapproximately 150 nm thick, and when the effective doping concentrationin the channel layer { (acceptor ion concentration)-(donor ionconcentration)+(concentration of trapping states and crystal defectsacting as acceptor ions)! for the case of NMOS; (donor ionconcentration)-(acceptor ion concentration)+(concentration of trappingstates and crystal defects acting as donor ions)! for the case of PMOS}is less than about 1×10¹⁸ cm⁻³, or when the threshold voltage of thethin film semiconductor device is less than approximately 4.5 V. Torestore the properties of transistors satisfying these conditions, it isimperative to control the surface of the underlevel insulator layer; andone way to do this is to use silicon oxide as the top layer in amutilayer underlevel protection layer composite.

It is necessary to have a sufficiently thick underlevel protection layerto prevent the diffusion of impurity ions from the substrate into thesemiconductor device, and this thickness is on the order of 100 nm as aminimum. Considering variations from lot to lot or from wafer to waferwithin a single lot, it is better to have a thickness greater than 200nm; and, if the thickness is 300 nm, the film can function sufficientlyas a protection layer. When the underlevel protection layer also servesas an interlevel insulator layer between IC elements or theinterconnects connecting such elements, a thickness of from 400 to 600nm is common. Since too thick of an insulating layer is a cause ofstress which can lead to cracking, however, a maximum thickness of about2 μm is preferable. Consideration of throughput, however, reduces themaximum thickness to 1 μm. For the case mentioned previously of acomposite interlevel protection layer comprising a bottom layer ofsilicon nitride and a top layer of silicon oxide, the same relationshold; and it is necessary to have a total thickness of 100 nm with eachlayer 50 nm thick. In the thin film semiconductor device of the presentinvention, the gate insulator layer is formed by CVD or PVD at atemperature below about 350° C. To obtain a clean MOS interface for thisprocess, the native oxide layer on the semiconductor layer surface isremoved immediately prior to gate oxide film formation. This nativeoxide removal step does not remove only the native oxide on the surfaceof the semiconductor layer, but also unfortunately removes part of theexposed underlevel silicon oxide layer surface not covered by thesemiconductor layer. Even after the native oxide removal step, theremust be 100 nm or more of the underlevel protection layer silicon oxidefor the layer to function properly. In other words, the minimumthickness of the silicon oxide layer is about 100 nm, and the minimumthickness of the silicon nitride is about 50 nm. For a thickness of lessthan 50 nm, the film islands do not link to form a complete film leavinggaps sporadically throughout the film. Since an underlevel protectionlayer loses its ability to prevent diffusive impurity penetration, it isnecessary to have a minimum film thickness of 50 nm even when severalfilms are used. As mentioned previously, the upper limit on thethickness of silicon nitride and silicon oxide films is 2 μm. Because anunderlevel protection layer film thickness of 300 nm is sufficient andthicker films actually are stressed leading to cracking or degradationof transistor properties, the ideal upper limit is approximately 500 nm.When several layers are combined in a composite layered structure, thestress conditions from each film are different; and if the thicknessesof all films are kept below about 500 nm, there should be no problems.

In general, silicon oxide films deposited by CVD or PVD at temperaturesless than about 350° C. have high internal stress. It is common torelieve a portion of such stress by high temperature thermal annealingfollowing deposition. In the low temperature process of the presentinvention, however, the maximum processing temperature must be keptbelow about 350° C. following gate insulator formation. Since it isdifficult to relieve stress in a silicon oxide film subjected to onlysuch a low temperature anneal, silicon oxide films thicker than about 2μm can lead to cracks in the substrate. Additionally, along withincreases in substrate size such as those greater than 300 mm×300 mm, itbecomes easier for stresses to accumulate and induce cracking in thesubstrate. The conditions are the same regardless of whether the siliconoxide film is a single layer or a is composite structure, and cracks aregenerated if the total silicon oxide film thickness is 2 μm or more. Inthe thin film semiconductor device of the present invention, anunderlevel protection layer of an insulating material is deposited on aportion of the substrate; and this is followed by fabrication of a fieldeffect transistor, comprising a semiconductor layer, gate insulator, andgate electrode, on top of the underlevel protection layer. This is thenfollowed by formation of an interlevel insulator layer between theinterconnects of the field effect transistor to achieve electricalisolation. In addition to at least the upper-most layer of theunderlevel protection layer being of silicon oxide, so is the MOSinterface part of the gate insulator; and it is normal to also usesilicon oxide in at least a portion of the interlevel insulator layer.Consequently, if the sum of the thicknesses of these three types ofsilicon oxide is less than 2 μm, formation of a thin film semiconductordevice by the low temperature process on large substrates is possiblewithout inducing cracking. Of course, it is possible to effectivelyprevent the generation of cracks if the sum of the thicknesses of theunderlevel protection layer, the gate insulator layer, and theinterlevel insulator layer is less than 2 μm.

As was explained previously in the reason for preferring the top layerof the underlevel insulator layer to be of silicon oxide, when using ahigh-quality semiconductor film for the active layer such as in the thinfilm semiconductor device of the present invention, control of theinterface between the semiconductor layer and the underlevel protectionlayer is important. Particularly when forming the semiconductor layerusing melt crystallization, it is desirable to have the surface of theunderlevel protection layer be as clean as possible. If the underlevelprotection layer surface is clean, this not only reduces the number ofinterface states between the semiconductor layer and the underlevelprotection layer, but also prevents particulate or other contaminantsfrom being incorporated into the semiconductor layer during the meltcrystallization step. Therefore, it is beneficial if the underlevelprotection layer and the semiconductor layer can be formed sequentiallyin the same piece of equipment. If the underlevel protection layer issilicon nitride, silicon oxide or a double layer of both, and thesemiconductor layer is a silicon or silicon germanium film, it ispossible to sequentially form such layers using a single PECVD reactor.If the mass production of thin film semiconductor devices is considered,the deposition chamber for these films are periodically cleaned; and itis necessary to remove the films which have adhered inside the PECVDdeposition chamber. If cleaning is not carried out and the filmscontinue to adhere, the films may eventually peel off and fall or leadto generation of abnormal microparticles which result in significantdecreases in production yield. On the other hand, however, during thecleaning step to remove deposited thin films from the depositionchamber, trace amounts of constituent elements from the cleaning vaporssuch as fluorine (F) and carbon (C) are sure to be left behind in thedeposition chamber. Under these conditions, the trace elements can beincorporated as impurities into the semiconductor film during thedeposition process and cause degradation of the transistor properties.Additionally, if the cleaning process is repeated after a set number ofsubstrates have been processed, the amount of impurities incorporatedinto substrates just after the cleaning step will be large while theamount incorporated into substrates just before the cleaning step willbe small. Put another way, the amount of impurities incorporated willdiffer from substrate to substrate; and it will not be possible toreliably produce excellent thin film semiconductor devices.Consequently, in the present invention, the cleaning process isperformed as part of the sequential deposition of the films describedearlier. In other words, the cleaning process is included with the filmdeposition process for each substrate. As the first step, prior toplacing the substrate in the PECVD reactor, the deposition chamber iscleaned of any films which were deposited during processing of theprevious substrate. Specifically, cleaning gases such as NF₃, CF₄, CHF₃,CH₂ F₂, and CH₃ F are introduced into the deposition chamber separately,or in combination with such reaction-controlling gases as oxygen (O₂),hydrogen (H₂), or ammonia (NH₃) ; or, as need be, with such inert gasesas helium (He), argon (Ar), or nitrogen (N₂); and a plasma is initiated.Thin films deposited in the deposition chamber are removed in this step.Following completion of this cleaning procedure, a vacuum is pulled onthe chamber to remove as much of the remaining gas vapors as possible.Next, in step two, a silicon nitride or silicon oxide passivation layerfor the remaining impurity elements is deposited. The impurity elements,in other words, are sealed in by the passivation layer. As for the caseof the underlevel protection layer, a passivation layer of more than 100nm will effectively prevent the penetration of the impurities. It isnecessary to completely remove this passivation layer after theprocessing of each substrate. Therefore, since making the film too thickwill slow down the manufacturing process by increasing both the time forremoval in step one and the time for deposition in step two, the upperlimit for the passivation film thickness is approximately 1 μm. Whensilicon nitride is used as the passivation film, ammonia (NH₃) andsilane (SiH₄, Si₂ H₆, etc.) are used as source gases. For silicon oxidepassivation layers, nitrous oxide (N₂ O) and silane are used. Followingplacement of the substrate in the deposition chamber in step three, theunderlevel protection layer is grown on the substrate in step four. Thedeposited layer functions as the underlevel protection layer on top ofthe substrate but functions as a second passivation layer on areas inthe deposition chamber away from the substrate. Because the underlevelprotection layer by itself is able to prevent the diffusion ofimpurities within the underlevel layer, when combined with thepassivation layer deposited in step two, it is able to almost completelyprevent the incorporation of impurities into the semiconductor layer.Following step four, the semiconductor layer is grown in step fivewithout breaking vacuum; and the processing of a single substrate iscompleted with removal of the substrate from the deposition chamber instep six. The same procedure is repeated for each subsequent substrate.By following this substrate processing procedure and sequentiallydepositing the underlevel protection layer and the semiconductor layer,it is possible to keep the interface between the underlevel protectionlayer and the semiconductor clean and fabricate excellent thin filmsemiconductor devices. Further, it is possible to keep the amount ofimpurities such as fluorine and carbon incorporated in the semiconductorlayer to a minimum. Even if there are minute amounts within the films,since it is possible to always keep the amount constant, the result isthe ability to reliably produce excellent thin film semiconductordevices in a high productivity process.

(2-2, Semiconductor Films in the Present Invention and the Source Gasesused to Grow Them)

In the present invention, semiconductor films are deposited on some typeof substrates. This is a feature common to all the following inventions.In addition to being applicable to single element films such as silicon(Si) and germanium (Ge), the following types of semiconductor films arealso possible: group IV compound semiconductor films such as silicongermanium (Si_(x) Ge_(1-x) : 0<x<1), silicon carbide (Si_(x) C_(1-x) :0<x<1), and germanium carbide (Ge_(x) C_(1-x) : 0<x<1) ; III-V compoundsemiconductor films such as gallium arsenide (GaAs), and indiumantimonide (InSb); II-VI compound semiconductor films such as cadmiumselenide (CdSe). The present invention is also applicable to highercompound semiconductor films such as silicon germanium gallium arsenide(Si_(x) Ge_(y) Ga_(z) As_(z) : x+y+z=1) as well as N-type semiconductorfilms in which donor elements such as phosphorous (P), arsenic (As), orantimony (Sb) have been added and P-type semiconductors in whichacceptor elements such as boron (B), aluminum (Al), gallium (Ga), andindium (In) have been added.

When semiconductor films are deposited by CVD in the present invention,the films are deposited using as source gases chemical speciescontaining the constitutive elements of the films. For example, when thesemiconductor film is silicon (Si), a silane such as monosilane (SiH₄) ,disilane (Si₂ H₆) , trisilane (Si₃ H₈) , or dichlorosilane (SiH₂ Cl₂) isused as a source gas. In the present invention disclosure, disilane andtrisilane are called higher silanes (Si_(n) H_(2n+2) : n is an integergreater than or equal to 2). If germanium (Ge) is the semiconductorfilm, germane (GeH₄) is used; and phosphine (PH₃) and diborane (B₂ H₆)can be used in addition if phosphorous (P) or boron (B) are to be addedto the semiconductor film. Although chemical species containing theconstitutive elements of the various types of films mentioned above canbe used as source gases, it is preferable to use hydrogenated species ofthe constitutive elements since some of the source gases will always beincorporated into the semiconductor film. For example, silicon filmsgrown from dichlorosilane (SiH₂ Cl₂) will always contain some chlorine(Cl) whether in small or large amounts; and this incorporated Cl canlead to the degradation of transistor properties when the silicon filmis used as the active layer in a thin film semiconductor device.Therefore, monosilane (SiH₄), a hydrogenated form of the constituentelement, is preferable over dichlorosilane. As high a purity as possiblefor the source gases, and dilution gases if need be, is desirable.Considering that costs increase as the technological difficulties inproducing high purity gases grow, a purity of 99.9999% or higher isdesirable. The background pressure of common semiconductor filmdeposition equipment is on the order of 10⁻⁶ torr, and the processpressure is from 0.1 torr to a few torr. Therefore, the ratio of theincorporation of impurities from the background pressure in the filmgrowth step is on the order of 10⁻⁵ to 10⁻⁶. The purity of the source ordilution gases is sufficient if it is equivalent to the ratio of theprocess pressure to the background pressure of the equipment using thegases. As a result, a purity of 99.999% or more (impurity ratio of1×10⁻⁵ or less) for gases flowing in the deposition equipment isdesirable in the present invention. If the purity is 99.9999% (impurityratio of 1×10⁻⁶ or less), there is absolutely no problem for use as asource gas; and, in the ideal case in which the purity is ten times thatof the ratio of the background pressure to the process pressure(99.99999% in the present example; impurity ratio of 1×10⁻⁷ or less),the incorporation of impurities from the gases need not even beconsidered.

(2-3, LPCVD Reactor used in the Present Invention)

The LPCVD reactor used in the present invention to deposit semiconductorfilms by the LPCVD process will be explained. The LPCVD reactor can beeither of the vertical or horizontal furnace type. Generally, thedeposition chamber is made of quartz or like material, and thesubstrates are placed near the center region of the deposition chamber.The outside of the deposition chamber is divided into multiple zoneswith heaters located in each zone. A uniform thermal region is createdat the desired temperature in the region around the center portion ofthe reaction chamber by using these heaters which can be independentlycontrolled. This is a so-called hot wall LPCVD reactor. By independentlycontrolling the individual heaters, it is possible to keep thetemperature variation within the uniform thermal region to within 0.2°C. Even though this temperature variation is very slight, it is alwayspresent, and is the leading cause of variations in film thickness.Additionally, since film thickness uniformity over one substrate isgiven preference over film thickness from substrate to substrate, it isdesirable to set the substrates parallel with respect to the radialheating direction of the heaters. For example, for a vertical furnaceLPCVD reactor, the semiconductor film thickness is more uniform when thesubstrates are placed approximately horizontal as opposed to when theyare placed vertically. Conversely, for a horizontal reactor, it isbetter to place the substrates approximately vertically. The sourcegases such as silane (SiH₄), disilane (Si₂ H₆), or germane (GeH₄) and,when need be, dilution gases such as helium, nitrogen, argon, andhydrogen enter the deposition chamber from a gas introduction port setup in a given direction. After depositing a semiconductor layer on themultiple substrates set in the central region of the deposition chamberas well as on the side walls of the deposition chamber, the gases areexhausted from a location opposite to that of the entrance port. Thegases are pumped through a gate valve or a conductance valve by apumping system which may consist of a turbomolecular pump and a rotarypump, for example. In the present invention, the pumping system consistsof a turbomolecular pump and a rotary pump; but combinations withmechanical booster pumps or dry pumps are also acceptable. Regardless ofwhether the reactor is vertical or horizontal, it is relatively simpleto achieve uniformity of the semiconductor film by basically aligningthe direction of gas flow in the deposition chamber with the directionnormal to the substrates set in the deposition chamber. In other words,in the case of a vertical reactor, it is preferable to have vertical gasflow since the substrates are placed approximately horizontally asmentioned previously. In a similar fashion, it is preferable to havehorizontal gas flow in a horizontal reactor because the substrates areplaced vertically. The LPCVD reactor used in the present invention is ahigh vacuum reactor with a background pressure in the 10⁻⁷ torr range.Consequently, it is possible to pump the inevitable outgassing from thesubstrates and substrate boat at a sufficient rate. The outgassingimpurity species from the substrate and boat, which include water andoxygen among others, are impediments to the growth of good semiconductorfilms. These outgassing impurities from the substrates and boat canbecome nuclei for the deposited film during the initial stages ofdeposition of a silicon or other type of semiconductor film. If theoutgassing is not exhausted sufficiently, there will be a large amountof adsorbed impurity gases on the substrate surface leading to thegeneration of many nuclei. Even when the semiconductor film iscrystallized by thermal annealing or laser irradiation followingdeposition, the presence of the many nuclei resulting from theoutgassing will result in the average grain size of the crystallizedfilm being small and cause a degradation in the transistor properties.Additionally, the trapping of outgassing impurities in the semiconductorfilm during growth leads to further decline in transistor properties. Asexplained in section (2-1), the film quality and surface roughness ofthe underlevel protection layer play an important role in suppressingthe generation of nuclei. At the same time, the deposition conditions ofthe semiconductor film must also be carefully controlled. Consequently,in addition to the regulation of the surface of the underlevelprotection layer in order to minimize the generation of nuclei, the useof an LPCVD reactor which can sufficiently pump the unavoidableoutgassing from the substrates and the surrounding surfaces isindispensable.

In LPCVD, semiconductor films are deposited on top of substrates usingthermal decomposition of the source gases. The two biggest issues inusing LPCVD to fabricate films on large substrates such as those 300mm×300 mm at relatively low temperatures while maintaining highproductivity are the deposition rate (DR) and the uniformity. Forexample, consider the deposition of a silicon layer on a large area,conventional, low cost glass substrate as mentioned previously. Forsubstrates 300 mm×300 mm or larger, distortion of the substrate from itsown weight will occur during film growth, regardless of the setting ofthe substrate, unless the deposition temperature is kept below about450° C. It goes without saying that such thermal distortion decreasesfor lower deposition temperatures; but for the distortion to decrease tosuch an extent that it has absolutely no effect on later process stepssuch as exposure during patterning, the deposition temperature must beless than about 430° C. Although semiconductor films such as silicon aredeposited at a low temperature of 425° C. using higher silanes likedisilane, decreasing the deposition temperature to such levels resultsin an extremely low deposition rate. Therefore, in order to obtain ahigh deposition rate even at such a low deposition temperature, thedeposition pressure is increased. Since gas density is proportional topressure, an increase in deposition pressure is equivalent to anincrease in the source gas density. The result is an increased rate oftransport of the source gases over the substrate surface and hence ahigher deposition rate. Unfortunately, however, using such a depositionprocedure causes the outer region of large substrates to be especiallythick; and the result is a deterioration in the film uniformity over thesurface of the substrate. The difference in film thickness between thecentral and outer portions of the substrate becomes conspicuous as thesubstrate size increases as well as when the deposition temperaturedecreases. One reason for this seems to be the generation of turbulenceat the substrate edge when the rate of source gas transport increases.As a result of the turbulence, a significantly large amount of gas istransported to only the edge regions with the final result being thatthe film is thicker along the edges as compared to the central portionof the substrate. Another reason seems to be that the transport rate ofthe gases to the center of the substrate decreases as the substrate sizeincreases. In other words, in order to obtain both a high depositionrate and uniform film thickness distribution at low temperatures lessthan 450° C. or less than about 430° C., it is essential to always havea high gas phase transport rate regardless of whether it is at the edgeor center of the substrate as well as to minimize the generation ofturbulence at the substrate edge. The inventor has performed a series ofexperiments which has shown that for a vacuum level characterized by asource gas partial pressure (disilane partial pressure if disilane isthe source gas) of between about 10 mtorr and 5 torr during deposition,the degree of turbulence and differences in transport rate are dependentupon the spacing, d, between substrates in the LPCVD reactor and can becontrolled to a certain degree. In the experiments, it was recognizedthat film thickness uniformity generally tended to improve as thesubstrate spacing d increased; and, further, that in order to obtain thesame level of uniformity for larger substrates, an even larger substratespacing was necessary. It appears that the uniformity improved as aresult of two phenomena. As the substrate spacing was increased by acertain degree, there was an increase in effective gas transport to thecenter region, and the difference in the amount of transport between thecentral and outer regions decreased. Additionally, the generation ofturbulence at the substrate perimeter also decreased. Specifically, inthe deposition temperature range of about 410° C. to 440° C., filmthickness uniformity can be improved by satisfying the conditions ofequation (1) shown below for substrates having an area greater than orequal to about 90000 mm² (substrate size of 300 mm×300 mm):

    d≧0.02×S.sup.1/2 (mm)                         (1)

For example, a substrate spacing d of 6 mm or more for 300 mm×300 mmsubstrates in a LPCVD reactor is good. Excluding the outer 1 cm of 300mm×300 mm substrates, the variation in film thickness was 3.4% when thesubstrates were set 7.5 mm apart in an LPCVD reactor for the followingdeposition conditions: actual deposition temperature of 425° C.,disilane flow rate of 200 sccm, helium flow rate of 1000 sccm, pressureof 1.2 torr, disilane partial pressure of 200 mtorr, and a depositionrate of 0.85 nm/min. (Film thickness variation is defined as(max-min)/(max+min) in which max and min are the maximum and minimumfilm thicknesses, respectively, in the 280 mm×280 mm area of thesubstrate which excludes the outer 1 cm around the perimeter.) Incontrast, a film thickness variation of 8.9% was obtained for the samesize substrates under the exact same deposition conditions when thesubstrates were placed 5 mm apart in the LPCVD reactor. As will beexplained in another section, the semiconductor film thickness has astrong influence on the performance of the thin film semiconductordevices. As long as the film thickness variation is less than about 5%,however, there is essentially no problems in variation of deviceperformance. In a similar manner, while a film thickness variation of4.2% was obtained when 360 mm×465 mm substrates were loaded in the LPCVDreactor with a spacing of 10 mm, the variation was 10.1% for a spacingof 7.5 mm. According to equation (1), a substrate spacing of greaterthan or equal to 8.2 mm is necessary for 360 mm×465 mm substrates; andthis is faithfully supported by the actual results. In this manner, areactor with a 120 cm wide uniform thermal zone can process 100substrates if the substrates are spaced 10 mm apart even if dummysubstrates are placed one each at the top and bottom (or front andback). As will be explained in the following section, the processingtime for one batch using the deposition procedure in this invention ison the order of 3 hours. Consequently, the processing time for a singlesubstrate (called the tact time in this invention) is one minute and 48seconds. When LPCVD reactor maintenance and down time is added, the tacttime becomes 2 minutes. In other words, it is possible to fabricate thinfilm semiconductor devices with good thickness uniformity and highproductivity.

As mentioned previously, a decrease in deposition temperatureaccompanies a decrease in deposition rate and makes the attainment ofuniformity difficult. If the deposition temperature is less than about410° C., equation (2) below replaces equation (1):

    d≧0.04×S.sup.1/2 (mm)                         (2).

If the substrates are set according to equation (2), good uniformity ispossible just as in the case of equation (1). As shown in FIG. 3A, whentwo substrates are placed back-to-back in a vertical configuration asone pair in a horizontal LPCVD reactor for deposition of a semiconductorfilm, the distance between adjoining pairs corresponds to the substratespacing d. Considering the previous example of 360 mm×465 mm substrates,it becomes possible to process 200 substrates in a single batch; and,further, the productivity is increased by a factor of two. A similarrelationship holds for vertical LPCVD reactors. In this case as well,two glass substrates are placed back-to-back as one pair and setapproximately horizontal. In other words, in one pair of glasssubstrates, the front of the lower substrate is facing down while thefront of the upper substrate is facing up. As for the case of thehorizontal reactor, the spacing between pairs of substrates correspondsto the substrate spacing d. See FIG. 3B. FIG. 4 shows one problem whichoccurs when large substrates are set horizontally in a hot-wall verticalLPCVD reactor. The center region of the substrate warps. This warpincreases as the substrate size increases and also increases for lowerglass strain point substrates. Conversely, high strain point glasssubstrates with good thermal resistance tend to have higher prices. Asshown in FIG. 3B, when setting several glass substrates in two-substratepairs in an LPCVD reactor, semiconductor films are deposited usingsubstrates with different strain points paired together with the highstrain point glass substrate used on the bottom. Because the high strainpoint glass has little warp, the low strain point glass substrate placedon top can also be made to have little warp using this technique. As aresult, it is possible to use even cheaper glass substrates. That is,pairing two glass substrates not only simply increases the productivityby a factor of two, but also allows the price of one LCD to be easilyreduced.

(2-4, LPCVD Semiconductor Film Deposition using the Present Invention)

As explained in the preceding section, a deposition temperature which isas low as possible is desirable for use with conventional, large areaglass substrates. A decrease in deposition temperature, however, alsomeans a decrease in deposition rate. In addition to the obvious decreasein productivity which results from the longer time necessary for filmdeposition with a lower deposition rate, a slower deposition rate alsohas deleterious effects on thin film semiconductor device performance.Put another way, in the fabrication of a good thin film semiconductordevice with a silicon-containing semiconductor layer by the lowtemperature process, when depositing the semiconductor film usingdisilane or a higher silane at a deposition temperature less than 450°C., especially less than or equal to approximately 430° C., if thedeposition rate is about 0.20 nm/min or higher, a high mobility thinfilm semiconductor device can be achieved. Further, if the depositionrate is about 0.60 nm/min or more, it is possible to decrease thevariation of transistor properties within a single substrate.Additionally, it is possible to fabricate a thin film semiconductordevice having good transistor properties using a poly-Si TFT in whichthe gate SiO₂ insulator layer is formed without the use of ECR-PECVD,and in which the pure silicon semiconductor film is deposited at adeposition temperature less than about 430° C. with a deposition rate ofabout 0.20 nm/min or more and is stable with respect to laser variationsduring melt crystallization. In fact, amorphous silicon films depositedat a deposition temperature of 400° C., disilane flow rate of 200 sccm,helium flow rate of 1000 sccm, pressure of 880 mtorr, disilane partialpressure of 147 mtorr, and a deposition rate of 0.12 nm/min as well asthose deposited at a deposition temperature of 425° C., disilane flowrate of 200 sccm, hydrogen flow rate of 200 sccm, pressure of 131 mtorr,disilane partial pressure of 65.5 mtorr, and a deposition rate of 0.19nm/min showed black spots throughout transmission electron micrographsand had small grain sizes following crystallization by RTA. As a result,the mobilities were also low when these films were employed as theactive layer in transistors. Although the details may not be certain,the following explanation may explain why black spots are seen intransmission electron micrographs and transistor properties degrade whenfilms are deposited with a deposition rate less than 0.20 nm/min.Perhaps if the growth rate is excessively slow, the surface of thegrowing film is exposed for a longer time to the gas phase with theresult being that more impurities from the background vacuum areincorporated. Therefore, the lower limit of the deposition rate dependson the background pressure in the LPCVD reactor. In other words, in anLPCVD reactor with a background pressure of 1×10⁻⁷ torr to 1×10⁻⁶ torrsuch as the one in the present invention, a good semiconductor film canbe deposited if the deposition rate is greater than or equal to 0.20nm/min. If the deposition rate becomes greater than or equal to 0.60nm/min, the effects from gas impurities disappear completely; and theamount of variation in transistor properties decreases as well. Further,as will be explained later, the optimum film thickness of thesemiconductor film for a thin film semiconductor device formed by LPCVDin the present invention is about 50 nm. Therefore, the deposition timeis on the order of 80 minutes for a deposition rate greater than orequal to 0.60 nm/min. Including the approximately 20 minutes necessaryto insert the substrates in the LPCVD reactor and pull a vacuum, theapproximately one hour for preliminary heating prior to film growth, theaforementioned one hour and 20 minutes for deposition, and theapproximately 20 minutes necessary for pulling a vacuum after filmgrowth and unloading the substrates, the total processing time for onebatch is about three hours. As shown in the previous section, the tacttime for processing a batch of 100 substrates is about two minutes; andextremely high productivity with a tact time of less than one minute canbe realized if the method of pairing two substrates together is used.

As has been explained in the preceding sections, in order to reliablyfabricate a high performance poly-Si TFT on large substrates with thelow temperature process, a silicon-containing semiconductor filmdeposition temperature of less than approximately 430° C., depositionrate greater than or equal to 0.6 nm/min, and a film thickness variationof less than about 5% over a large substrate are ideally required. Forthe case in which a higher silane such as disilane is used as the sourcegas in film formation using LPCVD, these conditions can be satisfied bya providing a relationship between the total surface area A (cm²) insidethe LPCVD reactor which can be covered with the semiconductor film andthe flow rate Q (sccm) of the higher silane introduced into thedeposition chamber during growth. In other words, by controlling thehigher silane flow rate per unit area, R (sccm/cm²) which is given by

    R=Q/A,

it is possible to satisfy the three ideal conditions mentioned above. Inthe growth of semiconductor films by LPCVD, the deposition temperaturemainly determines the chemical reaction rate at the surface of thesubstrates. On the other hand, there is a positive correlation betweenthe spatial concentration of the source gas and the rate of transport ofthe source gas in the gas phase. The concentration of the source gas Cis related to the source gas pressure P and the temperature T_(g) by

    C=P/kT.sub.g

in which k is the Boltzmann constant. When further increasing thedeposition rate with the deposition temperature set at a fixed value,that is, with the potential rate of surface reaction fixed, it is commonto increase the actual surface reaction rate by increasing the sourcegas pressure P to increase the rate of transport in the gas phase. But,as mentioned previously, increasing the deposition rate by increasingthe pressure unfortunately harms the film thickness uniformity. Whilethis fact is recognized, the pressure inside the deposition chamber P isrelated to the pumping speed S and the gas flow rate Q by

    P=Q/S.

Here there are three independent variables related by a single equationwhich results in the existence of two independent variables. In otherwords, if only pressure P is fixed, it is not possible to determine asingle physical condition. This means that for an identical pressure of100 mtorr, a system with a gas flow rate of 100 sccm and a pumping speedof 1 sccm/mtorr is completely different than a system with a gas flowrate of 1 sccm and a pumping speed of 0.01 sccm/mtorr. The inventornoticed this fact, and examined what kind of effect changes in thedeposition chamber pumping speed and the disilane source gas flow ratehad on the deposition rate and the film thickness uniformity whilekeeping the deposition temperature and deposition pressure constant. Theresults showed that even for a fixed deposition temperature anddeposition pressure, the deposition rate increased along with increasesin source gas flow rate; and further that the film thickness uniformitywas improved. Additionally, this relationship was recognized to bestrongly related to the total surface A inside the reaction chamber; andthat it is necessary to increase the source gas flow rate in proportionto the total surface area. This will be explained using FIG. 5.Amorphous silicon films were deposited in a 184.5 l vertical, hot wallLPCVD reactor with thirty five 300 mm×300 mm substrates placed adistance of 10 mm apart. The total surface area of the 35 substrates was63000 cm² since the area of one substrate (front and back) is 30 cm×30cm×2 or 1800 cm². Since the surface area of regions inside the reactorwhich can be coated with the semiconductor film during deposition is25262 cm², the total surface area which can be coated inside the reactoris

    A=63000+25262=88262 cm.sup.2.

Under these conditions, semiconductor films were deposited by flowingonly disilane into the deposition chamber at a deposition temperature of425° C. and a deposition pressure of 320 mtorr. The disilane flow ratewas varied from 50 sccm to 400 sccm while the deposition pressure waskept constant at 320 mtorr by varying the deposition chamber pumpingspeed by means of the LPCVD reactor pressure control unit. Thedeposition rate as a function of disilane flow rate under the givenconditions is shown by the circular data points and the "DR" solid linein FIG. 5 while the film thickness variation is shown by the square datapoints and the "V" dashed line. Since A is 88262 cm², the correspondingR values for the given flow rates, Q, are: Q=50 sccm, R=5.66×10⁻⁴sccm/cm² ; Q=100 sccm, R=1.13×10⁻³ sccm/cm² ; Q=200 sccm, R=2.27×10⁻³sccm/cm² ; and Q=400 sccm, R=4.53×10⁻³ sccm/cm². For R greater than2.27×10⁻³ sccm/cm², the deposition rate is essentially saturated; andthe surface reaction rate and the potential rate of surface reactionnearly agree. As discussed previously, for a fixed depositiontemperature and deposition pressure, a higher deposition rate ispreferred from both the viewpoint of productivity and the viewpoint ofsemiconductor film quality. When the deposition rate is high, the filmgrowth rate is large compared to the nucleation rate so that both thegrain size in the films after crystallization increases and the amountof impurity gases from outgassing incorporated into the film isdecreased. Both of these factors lead to improvement in thesemiconductor film quality and mean increases in mobility and decreasesin threshold voltage when these films are used as the active layer inthin film semiconductor devices.

Additionally, the decrease in impurity incorporation leads tosuppression of the poly-Si TFT off current. On account of these factors,a high deposition rate is preferred, and as seen in FIG. 5, this valuesaturates for R greater than or equal to 2.27×10⁻³ sccm/cm².Consequently, a value of the higher silane flow rate per unit area ofabout 2.27×10⁻³ sccm/cm² or more is preferred for the deposition ofsemiconductor films. The present experiment was performed in a verticalreactor with the gas introduced from the top and exhausted from thebottom. Using R=5.66×10⁻⁴ sccm/cm² resulted in a difference indeposition rate of 18% between the upper most substrate and the lowermost substrate. For R greater than or equal to about 1.13×10⁻³ sccm/cm²,this difference was practically unobservable; and, therefore, to obtainuniformity among substrates, an R value greater than or equal to about1.13×10⁻³ sccm/cm² is desirable. Further, as seen in FIG. 5, anR≧4.54×10⁻³ sccm/cm² is ideal since the variation within a singlesubstrate is 5% or less and gives a high deposition rate of 1.30 nm/min.

The source gas flow rate which corresponds to the total surface area inthe LPCVD reactor which can be covered with a semiconductor film mustalso be varied. In other words, the parameter which must be controlledis the higher silane flow rate per unit area, R. The exact sameexperiment described above was repeated with seventeen 235 mm×235 mmsubstrates placed a distance of 20 mm apart in the LPCVD reactor. Thesubstrate area was 23.5 cm×23.5 cm×2×17=18777 cm². This was combinedwith the reactor area of 25262 cm² to yield a total surface area of44039 cm². R values of about 5.66×10⁻⁴ sccm/cm², 1.13×10⁻³ sccm/cm²,2.27×10⁻³ sccm/cm², and 4.53×10⁻³ sccm/cm² correspond to higher silaneflow rates of 25 sccm, 50 sccm, 100 sccm, and 199 sccm, respectively.When the deposition rate and film thickness uniformity among substrateswas examined for the given disilane flow rates, behavior identical tothat found previously was confirmed. That is, in addition to thedeposition temperature and deposition pressure, the higher silane flowrate per unit area is a parameter necessary to unambiguously define thephysical system. According to the discovery above, an R value of about1.13×10⁻³ sccm/cm² or more is required for the deposition of asilicon-containing film at a deposition temperature of about 430° C. orless and a disilane partial pressure of about 100 mtorr or more. Forexample, for the deposition of a semiconductor film using one hundred400 mm×500 mm substrates set 15 mm apart in a 900 mm diametercylindrical deposition chamber, the substrate surface area is 400000 cm²; and the surface area inside the deposition chamber is about 56550 cm²,leading to a total surface area A of about 456500 cm². Therefore, theminimum necessary silane flow rate is given by the R value of 1.13×10⁻³sccm/cm² multiplied by the area A or 518 sccm. Similarly, a minimum flowrate of about 1050 sccm is necessary for semiconductor film depositionin the case in which there are one hundred 560 mm×720 mm substratesplaced 25 mm apart in a 1200 mm diameter chamber since A isapproximately 919500 cm² and R≧1.13×10⁻³ sccm/cm².

(2-5, Poly-Si TFT Channel Layer Thickness and Transistor Properties)

Here, the relationship between the semiconductor film thickness of theactive layer forming the channel in a poly-Si TFT thin filmsemiconductor device and the transistor properties will be discussed.Generally, the optimum film thickness for the semiconductor film to beused as the channel in a thin film semiconductor device depends stronglyon the fabrication method. This is because the film quality of thesemiconductor film varies widely with the film thickness. For example,in systems such as SOS (silicon on sapphire) and SOI (silicon oninsulator) in which the film quality does not, as a rule, depend on thefilm thickness, the transistor properties improve for thinnersemiconductor films. (Here, this principle is called the thin filmeffect.) This is because the inversion layer quickly spreads throughoutthe entire film thickness and the inversion layer can form readily inthe case of thin semiconductor films (the threshold voltage Vthdecreases). On the other hand, in thin film semiconductor devices usingpolycrystalline silicon films for the channel layer, the quality of thesemiconductor film is vastly different depending on the film thickness;and the mechanism mentioned above is much more complicated. Usually, thefilm quality of polycrystalline films worsens as the film thicknessdecreases. Specifically, in comparison to thick films, the grain size inthin films is smaller; and the number of internal grain defects andgrain boundary traps is simultaneously large. If the grain size issmall, the mobility of thin film semiconductor devices using such filmswill be low. Additionally, if the number of internal grain defects andgrain boundary traps is large, the spread of the depletion layer slows;and the threshold voltage Vth increases substantially. (Here, thisprinciple is called thin film degradation.) Ultimately, the thin filmeffect mentioned earlier and thin film degradation are competingprocesses. If the films are made thin but there is little change in filmquality (thin film degradation is small), the thin film effect isapplicable; and the transistor properties improve with thinner films.Conversely, if the films are made thin and there is a remarkabledegradation of the film quality (thin film degradation is large), thethin film effect is canceled; and transistor properties worsen forthinner films. In other words, depending on the magnitude of the filmquality dependence on the film thickness, the transistor properties mayimprove or may worsen with the use of thinner films. This dependence offilm quality on film thickness differs depending on fabricationtechnique; and also differs depending on film thickness. Consequently,the optimum semiconductor film thickness is completely differentdepending on the fabrication process of the thin film semiconductordevice; and the optimum thickness value must be determined for eachfabrication process.

(2-6, Optimum Film Thickness for the LPCVD--Crystallization Method)

Here, the optimum poly-Si TFT semiconductor film thickness for asemiconductor film fabricated by first using LPCVD at a depositiontemperature less than about 450° C., ideally about 430° C. or less,followed by crystallization for use in a low temperature process thinfilm semiconductor device of the present invention as described above isexplained. Using LPCVD at less than about 450° C., or less than or equalto about 430° C., the deposited film can coalesce to form a continuousfilm when the film thickness reaches approximately 10 nm or more. If acontinuous film does not form but only island regions exist, thesemiconductor "on" characteristics will be extremely poor because thefilm will still be discontinuous after crystallization regardless of theuse of melt crystallization or solid phase crystallization. In short,thin film degradation has overwhelmingly defeated the thin film effect.Therefore, the minimum film thickness for LPCVD--crystallization is onthe order of about 10 nm. As film thickness reaches about 20 nm or more,the transistor properties of melt crystallized films begin to improve.In the melt crystallization of semiconductor films, crystallizationoccurs with the gathering of peripheral semiconductor atoms around asingle central nucleus during the cooling solidification stage. Becauseof this, when film thickness is less than about 20 nm, even if acontinuous film forms immediately after deposition by LPCVD, cracks andcrevices are generated throughout the film following meltcrystallization; and transistor properties still do not improve. Inother words, in LPCVD--melt crystallization, thin film degradationdominates for films less than about 20 nm. As the film thickness reachesmore than about 20 nm, thin film degradation gradually decreases; andthe thin film effect begins to rival thin film degradation. Continuingthe trend in increased film thickness, transistor properties are bestfor film thickness between about 20 nm and about 80 nm. For thicknessesgreater than about 80 nm, the thin film effect predominates, andtransistor properties deteriorate along with increases in filmthickness. For semiconductor films about 30 nm or thicker, stable andreliable production is possible. Particularly with the advance of highprecision processing, the problem of contact failure between thesemiconductor film and the metallization can be decreased significantlyfor films approximately 30 nm or thicker when such processes as reactiveion etching (RIE) are used to open contact holes in the interlevelinsulator layer or the gate insulator layer. Usually the combinedthickness of the gate insulator layer and interlevel insulator layer isabout 600 nm; and if the film thickness variation for this thickness is±10%, or a total of 20%, the difference in film thickness between thethinnest insulator layer and the thickest insulator layer is on theorder of 120 nm. Since the selectivity ratio of RIE with respect tosemiconductor films is about 1:10, approximately 10-15 nm of thesemiconductor layer lying beneath the thinnest insulator layer isremoved during the opening of contact holes in the thickest insulatorlayer. Thus, even if about 15 nm is lost in such a manner during theopening of contact holes, the contact resistance is sufficiently low andthe problem of contact failure does not occur if the semiconductor filmthickness is about 30 nm or more. If the semiconductor film thickness isless than or equal to about 70 nm, the entire semiconductor layer can beuniformly heated and crystallization can proceed smoothly during meltcrystallization using a laser or other means. If, however, the filmthickness is greater than about 140 nm, only the upper portion of thelayer is melted during laser irradiation from above and the bottomportion of the layer retains amorphous regions. This adds to the thinfilm effect and the transistor properties deteriorate profoundly. Inother words, the maximum film thickness for the LPCVD--crystallizationmethod is on the order of 140 nm.

(2-7, Semiconductor Film Deposition Using the PECVD Process of thisInvention)

The method of forming the semiconductor film of the thin filmsemiconductor device of this invention using the PECVD process will bedescribed. The PECVD reactor used here is the capacitively-coupled type.The plasma uses industrial frequency rf waves (13.56 MHz) and isgenerated between two parallel plate electrodes. Of the two parallelplate electrodes, the lower parallel plate electrode has groundelectrical potential. The substrate on which the semiconductor film isto be deposited is placed on this electrode. The rf waves are suppliedto the upper parallel plate electrode. In addition, multiple gasintroduction ports exist in the upper parallel plate electrode, and thesource gases are supplied in a uniform laminar flow from this electrodeto the deposition chamber. The pressure at the time the film formationtakes place is from approximately 0.1 torr to approximately 5 torr. Thedistance between the parallel plate electrodes can be varied from about10 mm to about 50 mm.

After forming the underlevel protection layer on at least a portion ofthe substrate surface using an insulating material, such as a siliconoxide film, a semiconductor film is formed on top of this underlevelprotection layer. Ultimately, a thin film semiconductor device that usesthe semiconductor film as the transistor's active layer will beproduced. When a semiconductor film is to be deposited using the PECVDprocess, initially the underlevel protection layer is exposed to anoxygen plasma after the substrate has been placed in the depositionchamber of the PECVD reactor. The oxygen plasma is generated at anelectrode spacing of about 15 mm to 35 mm, a pressure of about 1.0 torrto 2.0 torr and an rf power density of approximately 0.05 w/cm² to 1w/cm². The temperature of the substrate is the same 250° C. to 350° C.as that during semiconductor deposition, and the oxygen plasma exposuretime is from about 10 seconds to one minute. After exposure to theoxygen plasma, the plasma is temporarily stopped and the depositionchamber is pumped down for 10 seconds to 30 seconds. If the vacuumpump-down takes place for 15 seconds or more, the level of the vacuum inthe deposition chamber will be 1 mtorr or lower. This takes place toprevent oxygen from being incorporated into the semiconductor filmduring semiconductor film deposition in the subsequent process step.After pulling the vacuum, the source gases that are used forsemiconductor film deposition, such as silane and hydrogen, are allowedto flow for 10 seconds to two minutes without generating a plasma.During this time, the conditions inside the deposition chamber, such asthe pressure and source gas flow rate, are the same as those used duringsemiconductor film deposition. Because this will result in the oxygen inthe deposition chamber being entirely replaced by the source gas, theincorporation of oxygen into the semiconductor film will be minimized.Further, if the period of gas flow is 30 seconds or more, thetemperature of the substrate is maintained at a constant temperature,and the semiconductor film can always be deposited under the sameconditions. In the thin film semiconductor device of this invention, theupper-most layer of the underlevel protection layer is composed of afilm such a silicon oxide, which has a low nucleation rate. Since thissilicon oxide film is formed using the CVD process or the PVD process,there will always be dangling bonds of the silicon. For this reason, ifthe semiconductor film is formed on top of the underlevel protectionlayer without some kind of pre-treatment, the dangling bonds would actas fixed electrical charges within the underlevel protection layer. Aspreviously stated, when the semiconductor film is thin, at or below afew hundred nanometers, these fixed electrical charges will causenegative influences on the thin film semiconductor device, such ascausing variations in the threshold voltage (Vth). By applying an oxygenplasma to the surface of the underlevel protection layer, the danglingbonds will bind with the oxygen atoms, and thus drastically reduce thefixed electrical charges within the underlevel protection layer. Inother words, even though the semiconductor film is made thin enough toimprove the semiconductor properties, instabilities in the properties,such as the Vth fluctuations caused by the underlevel protection layer,can be resolved. Moreover, the exposure to oxygen plasma will clean thesurface of the underlevel protection layer through the oxidationreaction (combustion) and restrain even further the nuclei generationrate at the initial stage of semiconductor deposition. This willincrease the purity of the semiconductor film, enlarge the areas thatform the deposited film, and enlarge the crystal grains that form thecrystallized semiconductor film. In terms of the properties of the thinfilm semiconductor device, this is manifest as a decrease in the offcurrent, a reduction in Vth, an improvement in the switching propertiesbecause sub- threshold swing will steepen, and an increase in themobility.

To improve the underlevel protection layer surface, in addition toexposure to an oxygen plasma, exposure to a hydrogen plasma is alsoeffective. That is, after the substrate on which the semiconductor filmis to be deposited is placed inside the PECVD reactor, the underlevelprotection layer on the substrate is first exposed to a hydrogen plasma.Then, without breaking vacuum, the semiconductor film is sequentiallyformed on top of the underlevel protection layer. The semiconductordeposition conditions use a lot of hydrogen, as in hydrogen 3000 sccmand monosilane 100 sccm. Furthermore, when the ratio of hydrogen is 10times or more that of silane, it is also possible to have continuousprocessing, from hydrogen plasma processing to semiconductor filmformation, without stopping the plasma. When the semiconductor filmdeposition conditions differ from the hydrogen plasma conditions, aswith monosilane 100 sccm in argon 7000 sccm, the plasma is temporarilyterminated after the hydrogen plasma processing; and, except for thefact that the plasma is not generated, it is desirable to have all otherprocess parameters the same as for the semiconductor film depositionconditions in order to create a stabilization period before thedeposition. Doing so will allow the substrate temperature to always beconstant when the semiconductor film is deposited. The hydrogen plasmaprocessing time is from 10 seconds to one minute, and the stabilizationperiod before the semiconductor film deposition is from 10 seconds totwo minutes.

Of the dangling bonds in the underlevel protection layer, there arethose that are terminated by oxygen, as in Si--*, and those that cannotbe terminated by oxygen, as in Si--O--*. Because hydrogen plasmaexposure can terminate these dangling bonds in the form of Si--H andSi--OH, an extraordinary effect can be observed in the decrease in thefixed electrical charges in the underlevel protection layer. Inaddition, because hydrogen plasma processing also has the effect ofetching and cleaning the underlevel protection layer surface, it alsoincreases the purity of the semiconductor film. Further, the adhesion ofthe underlevel protection layer and the semiconductor film improvesdramatically as a result of this cleaning. When a semiconductor film isformed using the PECVD process, crater-shaped holes can be generated inthe semiconductor film; and the film sometimes peels off depending onthe deposition conditions. This can be prevented, however, by processingwith hydrogen plasma.

When a semiconductor film is deposited, it is even more desirable toprocess with both oxygen plasma and hydrogen plasma. In other words,initially expose the surface of the silicon oxide underlevel protectionlayer to an oxygen plasma. At first, dangling bonds in the underlevelprotection layer will be terminated by the oxidation reaction. At thesame time, the surface will be cleaned by means of combustion, and thiswill suppress the rate of nuclei generation. Next, the oxygen plasma isterminated, and a vacuum is pulled for a period of from about 10 secondsto one minute to remove the oxygen within the deposition chamber. Theunderlevel protection layer is then sequentially exposed to a hydrogenplasma without breaking vacuum. Some dangling bonds that could not beterminated with the oxygen plasma will be terminated with the hydrogenplasma, and this will reduce the fixed electrical charges in theunderlevel protection layer to a minimum. Moreover, the surface willbecome even cleaner and at the same time the adhesion between thesemiconductor film and the underlevel protection layer will alsoimprove. After processing with the hydrogen plasma, vacuum pump-down andsubstrate heating will take place as needed; and the semiconductor filmis formed on the underlevel protection layer sequentially withoutbreaking vacuum. Doing this will not only bring about both thepreviously mentioned oxygen plasma effect and hydrogen plasma effect,but there will also be a clear reduction in the amount of oxygenincorporation into the semiconductor film since the hydrogen plasma stepcomes between the oxygen plasma step and the formation of thesemiconductor film. This will also allow a higher purity and higherquality semiconductor film to be obtained. As stated in section (2-1),for a melt crystallized semiconductor film, a clean underlevelprotection layer surface and control of the underlevel protectionlayer--semiconductor interface are particularly important. Consequently,the underlevel protection layer surface processing prior tosemiconductor film deposition is exceptionally significant.

Next, the processing after the semiconductor film has been formed usingthe PECVD process will be described. After the semiconductor film hasbeen formed on top of the underlevel protection layer, it is desirableto sequentially expose the semiconductor film to a plasma withoutbreaking vacuum. This will terminate the dangling bonds of thesemiconductor atoms, such as those of silicon. This is particularlyeffective when the film is formed under conditions in which there islittle hydrogen when the semiconductor film is deposited. For example,it is particularly effective in a system in which the amount of hydrogenis less than 50 percent of the gases that are introduced to thedeposition chamber, such as when the semiconductor film is depositedusing silane mixed with inert gases such as helium or argon. When asemiconductor film is deposited using such a system, a huge number ofdangling bonds will exist in the film. Since these dangling bonds areextremely chemically active, they will react with a variety ofimpurities and substances that exist within the atmosphere, or thesematerials can physically adsorb. If crystallization takes place in sucha condition using a laser, for example, the purity of the semiconductorwill decrease. In addition, the grains will become smaller since theadsorbed substances become the nuclei for crystal growth. Such problempoints can be easily eliminated by hydrogen plasma processing. In otherwords, a high purity, high-quality semiconductor film is in and ofitself unstable and can be contaminated by the atmosphere. Such a highpurity, high-quality film, however, can be stabilized by applying ahydrogen plasma after the film has been formed.

After the semiconductor film has been formed on top of the underlevelprotection layer, the same type of effect can also be accomplished bysequentially exposing the semiconductor film to an oxygen plasma withoutbreaking vacuum. When the semiconductor film is silicon or when siliconis the main component, oxygen plasma will form a silicon oxide film onthe semiconductor film surface. This oxide film is extremely stable.Compared to the semiconductor film surface, its ability to preventchemical and physical contaminant adsorption as well as diffusion ofsuch contaminants to the semiconductor film is excellent. That is, it isoptimal for protecting the semiconductor film from externalcontaminants. Further, because the oxidation takes place using an oxygenplasma in which the oxygen is quality-adjusted for high purity asopposed to oxygen in the atmosphere, the purity of the oxide film itselfis high. During subsequent crystallization, it is desirable to removethe oxide film. Yet, even if the oxide film is not removed, there arevirtually no problems with contaminants from the oxide film beingincorporated into the semiconductor film.

Ideally, after the semiconductor film has been deposited using a PECVDreactor, the film is exposed to a hydrogen plasma sequentially withoutbreaking vacuum, and this will inactivate most of the dangling bonds byhydrogen termination. Subsequent to this and again sequentially withoutbreaking vacuum, the semiconductor film is exposed to an oxygen plasma.This oxygen plasma will terminate any dangling bonds that were notterminated by the hydrogen plasma and can also be expected to form onthe surface of the semiconductor film a highly pure silicon oxide filmthat protects the semiconductor film from external contamination. Usingthis method of processing, not only will both the hydrogen plasma effectand the oxygen plasma effect be obtained, but also the effect of thedangling bond termination will increase and the amount of oxygenincorporated into the semiconductor film can be reduced. As a result,the semiconductor film purity after the crystallization will increasemore so than processing with the oxygen plasma alone, forming a betterthin film semiconductor device.

In the oxygen plasma exposure stage, as stated previously, regardless ofthe LPCVD and PECVD processes and even if the greatest amount of care istaken so that the semiconductor film becomes very pure, because an oxidefilm exists on the surface of the semiconductor film, the quality of thecrystallized film will decrease if oxygen is incorporated into thesemiconductor film during crystallization. This situation becomesparticularly serious in the case of melt crystallization such as bylaser irradiation.

A semiconductor film which has been carefully prepared using underlevelprotection layer surface preparation and the LPCVD and PECVD processes,as in this invention, requires that the same type of care be taken whencrystallizing. In other words, when a semiconductor film that forms theactive layer of a thin film semiconductor device is formed by meltcrystallization, such as by laser irradiation, it is desirable to removethe oxide film from the semiconductor film surface immediately prior tomelt crystallization. Doing so will allow the amount of oxygen from theoxide layer that gets into the semiconductor film to be reduced to aminimum when semiconductor film melting occurs. If the amount of oxygenthat gets into the semiconductor film is reduced, not only will thecrystallinity of the crystallized film increase, the defect density willdecrease and the transistor properties will greatly improve.

The processing method that makes the removal of the oxide filmimmediately prior to crystallization the easiest is one that uses ahydrofluoric acid solvent. Of course, the oxide film can be removed by agas-phase plasma process such as by using an NF₃ plasma. It is desirableto crystallize the semiconductor film immediately after removing theoxide film. If the semiconductor film is melt crystallized within twohours of the completion of the oxide film removal process, the amount ofoxygen that gets into the semiconductor film will be extremely low.

(2-8, Melt Crystallization of a Mixed-Crystallinity Semiconductor Film)

The thin film semiconductor device of this invention is most effectivefor top-gate poly-Si TFTs which are produced at temperatures of 350° C.or lower for all process steps from the formation of the gate insulatorlayer forward. As a consequence, if the semiconductor film formationstep can take place at a temperature of 350° C. or lower, all of theprocess steps will take place at 350° C. or lower. Currently, thethickness of the conventional glass substrates for LCDs is 1.1 mm. Ifthis were 0.7 mm, however, not only would the glass substrates becomecheaper, but also major benefits in the portability and the productionof the LCDs would arise because of the lighter-weight substrate. Sincethe density of glass is approximately 2.5 g/cm³, the weight of one sheetof glass with dimensions of 400 mm×500 mm×₋₋ 1.1 mm, for example, isabout 550 grams. If such glass substrates were processed in batches of100 sheets, the weight would be 55 kg, which would be a large load forproduction equipment and for transport robots. It goes without sayingthat if the thickness were 0.7 mm, the weight of a batch would decreaseto 35 kg, significantly reducing the load. For this reason, thinning ofthe glass substrates is desirable. Such a large thin film glass wouldbow significantly under its own weight, however, even at roomtemperature as shown in FIG. 4. And no matter what method were used withthe LPCVD process, a semiconductor film could not be formed. In otherwords, in order to use such a large piece of thin glass, thesemiconductor film would have to be formed using the PECVD process at atemperature of 350 degrees C or lower. Yet, in general, because of lowdensity of the films and the large amount of incorporated hydrogen, anamorphous semiconductor film formed using the PECVD process cannotcrystallize unless it first undergoes thermal annealing at 450° C.

When the inventor conducted various studies of semiconductor films fromthe PECVD process, it was discovered that when using the PECVD processat a deposition rate of about 0.1 nm/s or higher, a mixed-crystallinitysemiconductor film was produced and when this mixed-crystallinitysemiconductor film was exposed to laser light, melt crystallization waspossible even without the thermal annealing step mentioned above.Although the existence of crystal structure in this mixed-crystallinityfilm can barely be observed by Raman spectrometry, for instance, it isdifficult to call the film polycrystalline. In addition, the density isas low as the amorphous silicon formed using the PECVD process of theprior art, and hydrogen atoms are contained at just under 20 percent ofthe silicon atoms. The details of why such a film can be meltcrystallized in an orderly manner are not known. But it is believed thatit might be that the amorphous region is more easily melted than themicrocrystalline region, and that the microcrystals that float in themelted silicon liquid play the role of restricting the evaporation andthe scattering of the melted silicon liquid. Yet, even for amixed-crystallinity semiconductor film, it is difficult to meltcrystallize such a film with a deposition rate of about 0.1 nm/s orlower. As in the case with LPCVD in which it seems that film qualitydecreases for slower deposition rates as a result of the increased easeof impurity incorporation, the incorporation of impurities during filmgrowth in PECVD also seems to be the main factor leading to difficultiesin crystallization. In contrast to a background vacuum pressure in the10⁻⁷ torr range using LPCVD reactors, the background vacuum pressure isin the 10⁻⁴ torr range in PECVD reactors, and this may be the reasonthat high-speed film deposition can be observed using PECVD. Inaddition, if the deposition rate was 0.37 nm per second or higher, therewas an improvement in the adhesion between the semiconductor film andthe underlevel protection layer; and the generation of crater-shapedholes and film peeling virtually disappeared. Using the PECVD process, amixed-crystallinity silicon film can be obtained by setting the ratio ofthe hydrogen to monosilane flow rates to approximately 30:1.Alternatively, a mixed-crystallinity silicon film can be obtained bysetting the ratio of the flow rates of inert gases like argon to that ofthe chemical specie containing the constitutive elements of thesemiconductor film, such as monosilane, to less than about 33:1 (lessthan about 3 percent monosilane concentration). Based on experiments bythe inventor, hydrogen-monosilane system mixed-crystallinity can also bemelt crystallized without thermal annealing. The laser energy range inwhich melt crystallization proceeds well, however, is limited to severaltens of mJ/cm². In contrast to this, an argon-monosilane systemmixed-crystallinity silicon film will crystallize smoothly in a widelaser energy region, from 100 mJ/cm² to 350 mJ/cm². Therefore, anargon-monosilane system mixed-crystallinity silicon film is moresuitable as the semiconductor film of low temperature process poly-SiTFTs. The optimal argon to monosilane flow ratio for meltcrystallization is from about 124:1 (approximately 0.8 percentmonosilane concentration) to about 40.67:1 (approximately 2.4 percentmonosilane concentration).

(2-9, Optimum Film Thickness of PECVD--Crystallized Films)

Here, the optimum semiconductor film thickness for a poly-Si TFT, of alow temperature process thin film semiconductor device of the presentinvention described above, that was fabricated through crystallizationafter the semiconductor film was formed using the PECVD process at adeposition temperature of 350° C. or lower will be described. Among thelow temperature process thin film semiconductor devices of thisinvention that have been discussed above, here will be described. In thePECVD process, as in the LPCVD process, a film will become continuouswhen it reaches a thickness of 10 nm or more. However, the density ofthe semiconductor film obtained using the PECVD process is fromapproximately 85% to 95% of the film density obtained using the LPCVDprocess. For this reason, if the 10 nm semiconductor film of the PECVDprocess is crystallized, its film thickness will fall to about 9 nmafter crystallization. Thus, the minimum film thickness of aPECVD--crystallized film will be approximately 9 nm. As withLPCVD-crystallized films, if the film thickness is about 18 nm or more,the transistor properties of the melt crystallized film will begin toimprove. That is, with PECVD-melt crystallization, at 18 nm or less,thin film degradation is dominant; and, at 18 nm or higher, thin filmdegradation decreases, and the thin film effect becomes competitive.This will continue if the film thickness is between approximately 18 nmand approximately 72 nm and the transistor properties are optimum forfilms within this thickness range. If the film is thicker than 72 nm,the thin film effect takes control and the transistor properties willgradually deteriorate as the thickness of the film increases. If thesemiconductor film thickness is 30 nm or more, it is possible to havestable production of highly integrated thin film semiconductor devicesthat require fine geometry fabrication. In other words, with RIE,contacts holes can be opened up reliably without the appearance ofcontact failure. If the semiconductor film thickness immediately afterdeposition using the PECVD process is about 80 nm or less, the entiresemiconductor layer can be uniformly heated and crystallization canproceed smoothly during melt crystallization using a laser or othermeans. After crystallization, the thickness of the film will beapproximately 72 nm. If the semiconductor film immediately afterdeposition is about 150 nm thick or higher, only the upper portion ofthe layer is melted during laser irradiation from above and the bottomportion of the layer retains amorphous regions. This adds to the thinfilm effect and the transistor properties deteriorate profoundly. Inother words, the maximum film thickness for the PECVD--crystallizationmethod is on the order of about 135 nm after crystallization.

(2-10, MOS Interface, the Gate Insulator Layer and the ThermalEnvironment)

With this invention, the gate insulator layer is formed using CVD or PVDafter the semiconductor film crystallization is finished. No matter whatprocess is used to form the gate insulator layer, it is desirable thatthe insulator layer formation temperature be at 350° C. or lower. Thisis because it is important to prevent the thermal degradation of the MOSinterface and the gate insulator layer. This same thing applies to allof the subsequent process steps. All of the process steps after formingthe gate insulator layer have to be held to 350° C. or less. In general,a gate insulator layer formed using CVD or PVD has many dangling bondswithin the film; and the structure of the film is also unstable. Thisinvention terminates the dangling bonds by exposure to oxygen plasma. Inaddition, CVD silicon oxide films contain Si--OH groups. Dangling bondsthat have been terminated by such hydroxyl groups and oxygen plasmas areunstable in heat, easily dissociating in an environment of 350° C. orhigher. That is, dangling bonds such as Si--O--* and Si--* are generatedagain at the MOS interface and in the gate insulator layer. These becomeinterface states or fixed charges in the insulator layer and cause adeterioration of the transistor properties. In the prior art, hydrogenplasma processing took place for an hour in order to overcome this. Inthis invention, however, because all of the process steps after thesemiconductor film has been formed take place at 350° C. or less, suchthermal degradation does not occur. For this reason, hydrogenation isnot required. With this invention, a high performance, thin filmsemiconductor device can be produced easily and reliably. Although it isto be expected, the thermal degradation extends to the underlevelprotection layer as well. As described in section (2-1), thermaldegradation of the underlevel protection layer will lead to thedeterioration of the properties of the thin film semiconductor device.Although it is not as sensitive as the gate insulator layer, theinfluence is such that it cannot be ignored. For this reason,optimization of the thin film semiconductor device is achieved,theoretically, by having all processing steps, including thesemiconductor film deposition steps, take place at a temperature of 350°C. or lower. Doing so will avoid thermal degradation of both theunderlevel protection layer and the gate insulator layer. Processes thatcan form semiconductor films at temperatures of 350° C. or lower includePECVD and sputtering.

(2-11. The VHF-PECVD Reactor Used in this Invention)

First of all, FIGS. 2A-2B will be used to describe the generalconfiguration of the VHF-plasma enhanced chemical vapor depositionreactor (VHF-PECVD reactor) used in this invention. The PECVD reactor isa capacitively-coupled type, and the plasma is generated betweenparallel plate electrodes using a 144 MHz VHF power supply. The topdrawing in FIG. 2 is an overall perspective of the reaction chamber asviewed from above, a drawing of cross section A-A' is shown in FIG. 2B.Reaction chamber 201 is isolated from the outside by reaction vessel202, which is in a reduced pressure condition of from about 5 mtorr to 5torr during film formation. Inside of reaction vessel 202, lower plateelectrode 203 and upper plate electrode 204 are placed in mutuallyparallel positions. These two electrodes form the parallel plateelectrodes. The space between these parallel plate electrodes isreaction chamber 201. This invention uses parallel plate electrodes withdimension of 410 mm×510 mm. Since the distance between the electrodes isvariable from 10 mm to 50 mm, the volume of reaction chamber 201 variesfrom 2091 cm³ to 10455 cm³, depending on the distance between theelectrodes. The distance between the parallel plate electrodes can beset freely between 10 mm and 50 mm, as stated above, by moving theposition of lower electrode 203 up and down. Moreover, when set to adesignated electrode distance, the deviation of the electrode distanceover the 410 mm×510 mm plate electrode surfaces is a mere 0.5 mm. As aresult, the deviation in the electrical field strength that appearsbetween the electrodes is 5.0% or less over the plate electrodesurfaces; and an extremely uniform plasma is generated within reactionchamber 201. Substrate 205 on which thin film deposition is to takeplace is placed on top of lower plate electrode 203 and 2 mm of thesubstrate edge is held down by shadow frame 206. Shadow frame 206 hasbeen omitted from FIG. 2A to make the overall drawing of the PECVDreactor easy to understand. Heater 207 is installed within lower plateelectrode 203. The temperature of lower plate electrode 203 can beadjusted as desired from 25° C. to 400° C. Except for the peripheral 5mm, the temperature distribution within lower plate electrode 203 iswithin ±1.0° C. relative to the set-point temperature. Essentially, evenif the size of substrate 205 were 400 mm×500 mm, the temperaturedeviation within the substrate could be maintained to within 2.0° C. Forexample, if a conventional glass substrate (such as Corning Japan's#7059, Nippon Electric Glass Co., Ltd.'s OA-2, or NH Techno Glass'sNA35) were used as substrate 205, shadow frame 206 would hold substrate205 down to prevent it from deforming concavely by the heat from heater207 as well as to prevent unnecessary thin films from being formed onthe edges and back surface of the substrate. The reaction gas, which ismade up of source gases and additional gases as required, flows throughtube 208 and is introduced into upper plate electrode 204. It then flowsbetween gas diffusion plates 209 located inside upper plate electrode204, and flows from the entire surface of the upper plate electrode intoreaction chamber 201 at a virtually uniform pressure. If film formationis taking place, some of the reaction gas will be ionized when it exitsthe upper plate electrode and cause a plasma to be generated between theparallel plate electrodes. From a part to all of the reaction gas willparticipate in film formation. Residual reaction gas that has notparticipated in film formation and gases formed as a result of the filmforming chemical reaction will become discharge gases and be dischargedthrough exhaust port 210 which is in the top of the peripheral sectionof reaction vessel 202. The conductance of discharge port 210 issufficiently large compared to the conductance between the parallelplate electrodes. The desired value is one that is 100 times or more ofthe conductance between the parallel plate electrodes. In addition, theconductance between the parallel plate electrodes is even sufficientlylarger than the conductance of gas diffusion plate 209, and that desiredvalue is also 100 times or more of the conductance of gas diffusionplate 209. Through such a configuration, reaction gas can flow into thereaction chamber virtually uniformly from the entire surface of thelarge 410 mm×510 mm upper plate electrode; and, at the same time,discharge gas will be discharged in all directions from the reactionchamber in an even flow. The flow rates of the various reaction gases totube 208 will be adjusted to their designated values by mass flowcontrollers. In addition, the pressure within reaction vessel 202 willbe adjusted to the desired value by conductance valve 211, which islocated at the exit of the discharge port. A pumping system, such as aturbomolecular pump, is located on the exhaust side of conductance valve211. In this invention, an oil-free magnetic levitation typeturbomolecular pump is used as part of the pumping system, and thebackground vacuum within reaction vessels such as the reaction chamberis set to the 10⁻⁷ torr level. In FIGS. 2A-2B, arrows are used to showthe general flow of the gas. Both reaction vessel 202 and lower plateelectrode 203 are at ground potential. These and upper plate electrode204 are electrically isolated by insulation link 212. When a plasma isgenerated, for example, 144 MHz VHF waves that are generated from VHFwave oscillation source 213 are amplified by amplifier 214, pass throughmatching circuit 215, and are applied to upper plate electrode 204.

As stated above, because the PECVD reactor used in this invention hasvery sophisticated intra-electrode interval control and uniform gasflow, it is a thin film formation reactor that is able to handle largesubstrates of 400 mm×500 mm in size. However, by merely adhering tothese basic concepts, it can easily handle further enlargements in thesubstrate. Actually, it is possible to produce a reactor that can handleeven larger substrates of 550 mm×650 mm. In addition, in this invention,a common 144 MHz VHF wave frequency was used. Of course, VHS waves usingother frequencies may also be used. For example, VHF waves from 100 MHzto 1 GHz may all be used. On the other hand, if the rf frequency is from10 MHz to several hundred MHz (VHF), it is possible to generate a plasmabetween the parallel plate electrodes. Therefore, frequencies such as27.12 MHz, 40.68 MHz, 54.24 MHz and 67.8 MHz, which are whole numbermultiples of the industrial rf frequency (13.56 MHz) may be used. Inother words, by changing VHF wave oscillator 213, amplifier 214, andmatching circuit 215 of the PECVD reactor used in this invention, aplasma using electromagnetic waves of a desired frequency can be easilygenerated. In general, in the case of an electromagnetic wave plasma, ifthe frequency is increased, the electron temperature within the plasmawill increase and radicals can be easily created. For this reason, aswill be explained later, even if the temperature of the substrate is aslow as approximately 340° C., the deposited film will already be in apolycrystalline silicon condition immediately after deposition. Thus,poly-Si TFTs can be easily fabricated even without specialcrystallization process steps.

(2-12, Semiconductor Film Formation and the Gases Used for FormationWhen Using VHF-PECVD and Microwave PECVD)

One of the characteristics of this invention is that a film deposited byVHF-PECVD or microwave PECVD is polycrystalline immediately afterdeposition (an as-deposited film). It is extremely difficult to make apolycrystalline as-deposited film using normal PECVD processing. Sincethe substrate temperature is less than 400° C., the mobility of sourcematerials such as silane on the surface of the growing film decreases;and the selectivity of the source material for the polycrystalline stateas opposed to the amorphous state is lost. This invention eliminatesthis deficiency in the PECVD method by diluting source materials usingnoble gas elements and by using a VHF plasma or microwave plasma, bothof which are capable of raising the electron temperature. To form apolycrystalline film in the as-deposited state, radicals and ions of thenoble gas elements, such as helium (He), neon (Ne), and argon (Ar), aregenerated, without generating radicals and ions of the source materials,and must carry energy to the surface of the substrate. Because radicalsand ions of source materials cause vapor phase reactions or react theinstant they arrive at the substrate surface, selectivity is lost,thereby preventing polycrystalline growth. For these reasons, thegeneration of such radicals and ions within a plasma must be avoided atall costs. The source materials are carried to the surface of thegrowing film in an inactive state and become adsorbed there.Subsequently, if energy for reaction is supplied, such as by a dilutegas, a polycrystalline film will be formed in the as- deposited state.Consequently, dilution of the source gas is desired, and this gives riseto the necessity of selecting as the dilution gas a gas that promotesreaction of the source materials on the substrate surface. It goeswithout saying that the noble gas elements are composed of individualatoms, and, for this reason the ionization potential spectrum is verysimple. For example, the monovalent ionization potential of helium is24.587 eV, while the divalent ionization potential is only 54.416 eV.Further, the monovalent ionization potential of neon is 21.564 eV, whilethe divalent ionization potential is 40.962 eV. The monovalentionization potential of argon is 15.759 eV, while the divalentionization potential is 27.629 eV, and the trivalent ionizationpotential is 40.74 eV. Therefore, when a small amount of sourcematerials is diluted in helium and a plasma is generated, most of theionized helium will be 24.587 eV monovalent ions. When a small amount ofsource materials are diluted in neon and a plasma is generated, the neonwill be ionized into mainly monovalent ions of 21.564 eV. For argon,although both the monovalent ions and divalent ions are dominant, argonradicals and ions are effectively generated even when the sourcematerial is not diluted by a large amount of argon because theionization energy is relatively low. In contrast to this, there ishydrogen, widely used as a dilution gas in the prior art, in which morethan ten different ionization potentials exist between 15 eV and 18 eVfor the ionization potential of the hydrogen molecules. For this reason,in contrast to noble gas elements such as helium which form plasmascontaining one or two energies (laser light if referred to in terms oflight), molecular gases such as hydrogen form plasmas containing amixture of energies (white light if referred to in terms of light). Justas laser light will transport energy more effectively than white light,energy is transported to the substrate surface more effectively when thesource gas is diluted by a noble gas element. In addition to the noblegas elements of helium, neon and argon, krypton (Kr) and xenon (Xe) mayof course also be used as dilution materials during the deposition ofsemiconductor films. On the other hand, since VHS and microwave plasmashave high average electron temperatures within the plasma, the radicalgeneration efficiency can be increased at relatively low power. In otherwords, since high power is not necessary, these plasmas generate fewhigh energy ions, and resulting film damage is kept to a minimum.Further, a high radical generation efficiency also increases the filmgrowth rate. If this invention were also carried out using the 13.56 MHzrf plasma used widely in the prior art, the film formation rate would beextremely slow, less than several Å/min, making it absolutely unsuitablefor utilization. Moreover, a very slow film formation rate will beharmful, reducing the quality of the film. Which is to say that it isprecisely because VHF plasmas and microwave plasmas are used that thisinvention can be attained. In this sense, this invention can be veryeasily achieved by also using microwave PECVD, having a frequency aninteger multiple of 2.45 GHz. And with such systems, there is an evengreater degree of freedom in film formation conditions than inVHF-PECVD, meaning a semiconductor film with even better crystallinitycan be deposited with greater ease.

(2-13, Optimum Film Thicknesses for VHF-PECVD and Microwave PECVDAs-Deposited Films)

When placing a film in the polycrystalline state immediately afterdeposition (as-deposited) using VHF-PECVD or microwave PECVD, the filmquality for film thicknesses ranging from 0 to 500 Å will be extremelypoor compared to normal crystallized films. The film will consist ofsmall, island-shaped crystalline grains in a sea of amorphous material,have a very low degree of crystallinity, and contain a large number ofdefects. From 500 Å to 1000 Å, the ratio of crystal grains to theamorphous material will increase. From about 1000 Å to 1500 Å, thesemiconductor surface will be generally covered with crystal grains; andthe amorphous components on the surface will almost disappear. Fromabout 1500 Å to 2000 Å, the size of the crystal grains will graduallyincrease along with the film thickness. At 2000 Å or higher, the filmwill grow while the crystal grains maintain approximately the sameshape. The film thickness dependency of the transistor properties willalso change in response to changes in the film quality relative to thefilm thickness. At 2000 Å or higher, because the film quality willexhibit virtually no change (because there is almost no thin filmdegradation), the thin film effect is active; and the thinner the film,the better the transistor properties become. At film thicknesses of 2000Å to 1500 Å, thin film degradation will begin to take effect. Yet, asbefore, the thin film effect will remain dominant. Although this will bemore lax than at 2000 Å or higher, even here, the thinner the film thebetter the transistor properties become. Between 1500 Å and 200 Å, thinfilm degradation and the thin film effect become competitive andtransistor properties in the on condition reach their maximum values.With a film thickness of less than 200 Å, thin film degradationovercomes the thin film effect, and the thinner the film, the poorer thetransistor properties. Put another way, in the case of this invention,transistor properties are the best at semiconductor film thicknessesfrom 200 Å to 1500 Å, but ideally between 400 Å to 1300 Å. Until thispoint, the discussion has been about transistor properties in the onstate; but the leak current will also vary with the thickness of thefilm. The principles of off state leakage in thin film semiconductordevice are not well understood. In this invention, the principles areunclear; but, if the film thickness is 1000 Å or more, there is a strongpositive correlation between the film thickness and off state leakage.The thicker the film, the larger the off state leakage. If the filmthickness is less than 1000 Å, the correlation weakens and becomesindependent of the off state leakage. In other words, between 0 and 1000Å, the off state leakage current is almost consistently at a minimum.Consequently, the on state transistor properties are best, and the filmthicknesses in which the off state leakage is the smallest are from 200Å to 1000 Å, but ideally from 400 Å to 1000 Å. When the thin filmsemiconductor device of this invention is used in an LCD, it isdesirable to consider the effects of light exposure on the off stateleakage current. Light exposure will cause an increase in the off stateleakage current in thin film semiconductor devices. This is called theoptical leakage current. Having a sufficiently small optical leakagecurrent is a condition for a good thin film semiconductor device. In thecase of the thin film semiconductor device of this invention, theoptical leakage current is proportional to the film thickness. From theperspective of reliable production and optical leakage currentcoexisting, it is desirable to have a film thickness from about 100 Å to800 Å. In a case in which the off state leakage and optical leakage areimportant, such as when using a thin film semiconductor device for thepixel switching element of an LCD, it is desirable to have asemiconductor film thickness from 100 Å to 700 Å. Moreover, when it isnecessary to give even stronger consideration to on current, the optimumthickness is from 200 Å to 800 Å. A system that would satisfy allconditions would have a thickness from 400 Å to 800 Å, but ideally from600 Å to 800 Å. Further, it is normally quite difficult to activateimplanted ions in the source and drain regions at a low temperature of350° C. or lower as happens with this invention. This is the reason thatto carry out activation in a stable manner, a lower limit must be setfor the semiconductor film thickness. With this invention, the desiredvalue is 300 Å or higher. If an LDD structure is to be utilized, athickness of 500 Å or higher is desired.

(2-14, Crystallization of the Semiconductor Film through VHF-PECVD andMicrowave PECVD)

As described in detail in section (2-12), although a polycrystallinefilm in the as-deposited state can be obtained easily using VHF- PECVD,the film quality is not as good as a crystallization film. On the otherhand, it is difficult to crystallize a film obtained from the normalPECVD process as long as it has not been dehydrogenated or carefullyannealed. In contrast, a semiconductor film from VHF-PECVD or microwavePECVD can be very easily crystallized using RTA or VST-SPC, or be meltcrystallized such as by laser irradiation. Since most of the film willalready be in an as-deposited crystalline state and residual amorphouscomponents will be limited, crystallization of residual amorphouscomponents can be achieved by means of a relatively low energy supply.Also, even when melt crystallization progresses using high energy, thepolycrystalline components play the role of preventing the evaporationand scattering of semiconductor atoms. Thus, crystallization can proceedsmoothly without semiconductor film damage, surface roughness, materialloss and other problems. Ultimately, it can be said that rather thanhaving a film obtained through the VHF-PECVD process or the microwavePECVD process as the active area of a thin film semiconductor device inthe as-deposited state, it is more suitable to have such a film be thefirst semiconductor layer when producing low temperature poly-Si TFTs inwhich the highest temperature of the process step is 350° C. or lowerusing melt crystallization. Put differently, a high-performance thinfilm semiconductor device can be produced by forming a semiconductorfilm on top of an insulating substance using the VHF-PECVD process orthe microwave PECVD process and then crystallizing this film using solidphase crystallization, such as RTA or VST-SPC, or crystallizing it usingmelt crystallization, such as by laser irradiation, and then having thesubsequent process steps take place at 350° C. or lower.

Films deposited by VHF-PECVD or by microwave PECVD have quality closerto that of films deposited using LPCVD than to films deposited by PECVD.For this reason, the relationship between the transistor properties andsemiconductor film thickness obtained when producing a thin filmsemiconductor device through crystallization becomes equivalent to therelationship possessed by a thin film semiconductor device produced bythe LPCVD process. In contrast to semiconductor films produced by theLPCVD process, however, which show almost no reduction in film thicknessbefore and after crystallization, some slight reduction can be found inVHF-PECVD and microwave PECVD films. Therefore, when crystallizing suchfilms to produce thin film semiconductor devices, the discussion insection (2-6) can be applied as is by considering the semiconductor filmthickness after crystallization to be the same as the film thickness ofa film from the LPCVD--crystallization method.

As discussed in the foregoing, using this invention, high-qualitysemiconductor films comprised of polycrystalline silicon films andothers can be easily formed at low temperatures of less than about 450°C. and 430° C. or lower. Thus, this invention greatly improves theproperties of thin film semiconductor devices as well as brings aboutreliable mass production. To be specific, it has the effects that aredescribed below.

Effect 1). Since the processing temperatures are below about 450° C.,low-cost glass can be used and it is possible to lower the price of theproducts. Additionally, since it is possible to prevent the warpage ofthe glass under its own weight, it is easily possible to increase thesize of liquid crystal displays (LCDs).

Effect 2). Since the processing temperatures are approximately 350° C.or less, there is no thermal degradation of the underlevel insulatorlayer or gate insulator layer; and it is possible to easily producehigh-performance thin film semiconductor devices with excellentreliability.

Effect 3). Laser irradiation can be applied uniformly over the entiresubstrate. The result of this is that the uniformity of each lot isimproved, and reliable production has become possible.

Effect 4). The formation of self-aligned TFTs in which the gateelectrode is aligned with the source and drain by ion doping andsubsequent low temperature activation at approximately 300° C.-350° C.has become remarkably easy. As a result, it has become possible toreliably activate impurity ions. Additionally, it has become possible toeasily and reliably fabricate lightly doped drain (LDD) TFTs. BecauseLDD TFTs have been realized by low temperature process poly-Si TFTs, ithas become possible to decrease TFT element size and off leak currents.

Effect 5). In the prior art, only low temperature poly-Si TFTs havingSiO₂ made by ECR-PECVD showed good transistor characteristics. Usingthis invention, however, this has become possible using conventionalPECVD reactors. Consequently, practical gate insulator layer fabricationequipment applicable to large substrates and suitable for massproduction has been achieved.

Effect 6). Thin film semiconductor devices with higher on currents andlower off currents than those produced by the prior art have beenobtained. Additionally, the non-uniformity in these values has beendecreased.

Effect 7). When using low price, conventional glass, it has becomepossible to form underlevel protection layers which effectively preventthe incorporation of impurities from the substrate into thesemiconductor film and simultaneously act as the underlevel protectionlayer for thin film semiconductor devices showing optimum electricalproperties. Also, the degradation of the electrical properties of thinfilm semiconductor devices as a result of stress from the underlevelprotection layer and the generation of cracks in the thin filmsemiconductor devices have been avoided.

Effect 8). The incorporation of constitutive elements such as fluorine(F) and carbon (C) from cleaning vapors into the semiconductor filmswhen such films are formed by plasma enhanced chemical vapor deposition(PECVD) has been prevented. As a result, the amount of impurities amongsubstrates can always be kept to a minimum and it has become possible toreliably fabricate excellent thin film semiconductor devices.

Effect 9). Even when depositing semiconductor films by low pressurechemical vapor deposition (LPCVD) at low temperatures less than about450° C., it has become possible to simultaneously achieve uniformity,both within a single substrate and among different substrates, and asuitable deposition rate. Therefore, it is possible to accommodateincreasing substrate size; and it has become possible to mass producelarge-area LCDs.

Effect 10). Three types of variation in electrical properties of thinfilm semiconductor devices are recognized: variation within a singlesubstrate, variation among substrates within the same lot, and variationfrom lot to lot. Using this invention, however, all three types ofvariation can be controlled. The variation among lots processed by PECVDhas been particularly significantly improved.

Effect 11). Even when the semiconductor film is grown by PECVD, goodadhesion between the semiconductor film and the underlevel protectionlayer can be achieved. In other words, problems such as the generationof numerous crater-shaped holes in the semiconductor film and peeling ofthe films have been avoided.

Effect 12). Even without special crystallization processing, poly-SiTFTs can be fabricated reliably on large-area substrates by lowtemperature processing less than or equal to about 350° C.

BRIEF EXPLANATION OF THE FIGURES

FIGS. 1A-1D are element cross-sectional views for each step in thefabrication of a thin film semiconductor device showing one practicalexample of this invention;

FIGS. 2A-2B show the PECVD reactor used in this invention;

FIGS. 3A-3B show the deposition chamber and the deposition chamberinterior of the LPCVD reactor of this invention;

FIG. 4 explains the substrate warpage resulting from a thermalenvironment; and

FIG. 5 explains the results of this invention.

THE BEST SYSTEMS FOR IMPLEMENTING THIS INVENTION

This invention is explained in further detail with reference to theaccompanying figures.

EXAMPLE 1

FIGS. 1A-1D show cross-sectional views of the fabrication process for athin film MIS field effect transistor.

In Example 1, a 235 mm×235 mm sheet of non-alkaline glass (OA-2,manufactured by Nippon Electric Glass Co., Ltd.) was used for substrate101, though the type and size of the substrate are irrelevant for anysubstrate able to withstand the maximum processing temperature. First,silicon dioxide film (SiO₂ film) 102, which serves as the underlevelprotection layer, is formed on substrate 101 by means of atmosphericpressure chemical vapor deposition (APCVD), PECVD, sputtering or othermeans. In APCVD, the SiO₂ layer can be deposited using monosilane (SiH₄)and oxygen as source gases at a substrate temperature of between about250° C. and 450° C. In the PECVD and sputtering methods, the substratetemperature can be anywhere from room temperature to 400° C. In Example1, a 2000 Å SiO₂ film was deposited at 300° C. by APCVD using SiH₄ andO₂ as source gases.

Then, an intrinsic silicon layer, which later becomes the active layerof the thin film semiconductor device, was deposited to a thickness ofapproximately 500 Å. The intrinsic silicon layer was deposited over 58minutes at a temperature of 425° C. by a high vacuum LPCVD reactorhaving a 200 sccm flow of disilane (Si₂ H₆) as the source gas. The highvacuum LPCVD reactor used in Example 1 has a capacity of 184.51.Seventeen substrates were inserted facedown in the reaction chamber,which was maintained at 250° C. After the substrates were inserted, theturbomolecular pump was started. After the pump reached steady-statespeed, a two-minute leak test was performed. The leak rate fromoutgassing and other sources at this time was 3.1×10⁻⁵ torr/min. The250° C. insertion temperature was then raised to a depositiontemperature of 425° C. over a period of 1 hour. For the first 10 minutesafter heating was initiated, no gas was introduced into the reactionchamber and heating was performed in a vacuum. The ultimate backgroundpressure reached in the reaction chamber 10 minutes after the onset ofheating was 5.2×10⁻⁷ torr. During the remaining 50 minutes of theheating period, nitrogen gas having a purity of at least 99.9999% wascontinuously introduced at the rate of 300 sccm. The equilibriumpressure in the reaction chamber at this time was 3.0 xx 10⁻³ torr.After the deposition temperature was reached, the source gases, Si₂ H₆and 99.9999% pure helium (He) for dilution, were introduced at the flowrates of 200 sccm and 1000 sccm, respectively; and the silicon film wasdeposited over a period of 58 minutes. The pressure immediately afterSi₂ H₆ and other gases were introduced into the reaction chamber was 767mtorr; and the pressure 57 minutes after these source gases wereintroduced was 951 mtorr. Silicon films obtained in this way were 501 Åthick; and, except for the 7 mm periphery of the substrate, thethickness of the film varied less than ±5 Å over the 221 mm×221 mmsquare region. In Example 1, the silicon layer was formed as describedby means of LPCVD, but PECVD and sputtering can also be used. In thePECVD and sputtering methods, silicon film deposition temperature may beset anywhere between room temperature and approximately 350° C.

Silicon films obtained in this manner are high-purity a-Si films. Next,this a-Si layer is crystallized by irradiating it for a short period oftime with either optical energy or electromagnetic energy, therebychanging it into polycrystalline silicon (poly-Si). In Example 1, thea-Si layer was irradiated using a xenon chloride (XeCl) excimer laser(wavelength of 308 nm). The laser pulse width at full-width, halfmaximum intensity was 45 ns. Since this irradiation time is extremelybrief, the substrate is not heated when the a-Si is crystallized intopoly-Si, hence substrate deformation does not occur. Laser irradiationwas performed in air with the substrate at room temperature (25° C). An8 mm×8 mm square area is irradiated during each laser irradiation, andthe irradiated area is shifted by 4 mm after each irradiation. At first,scanning is performed in the horizontal direction (Y direction), andthen the substrate is then shifted 4 mm in the vertical direction (Xdirection). It is then moved 4 mm more in the horizontal direction,where it is again scanned. Thereafter these scans are repeated until theentire surface of the substrate has been subjected to the first laserirradiation. The energy density of this first laser irradiation was 160mJ/cm². After the first laser irradiation was completed, a second laserirradiation was performed over the entire surface at an energy densityof 275 mJ/cm². The scanning method used for the second irradiation isidentical to that used for the first laser irradiation; scanning isperformed while shifting the 8 mm×8 mm square irradiation area in 4 mmincrements in the Y and X directions. This two-stage laser irradiationprovides the means for uniformly crystallizing the a-Si to form poly-Siover the entire substrate. While an XeCl excimer laser was used as theoptical energy or electromagnetic energy in Example 1, other energysources may be used provided the energy irradiation time is less thanseveral tens of seconds. For example, irradiation may also be performedusing an ArF excimer laser, XeF excimer laser, KrF excimer laser, YAGlaser, carbon dioxide gas laser, Ar laser, dye laser or other laser, aswell as by an arc lamp, tungsten lamp or other light source. When usingan arc lamp to irradiate the a-Si layer to transform it into poly-Si,output of about 1 kW/cm² or greater and an irradiation time of about 45seconds is used. Even at the time of this crystallization, the energyirradiation time is short, so problems such as deformation and crackingcaused by heating the substrate do not occur. This silicon film was thenpatterned and channel region semiconductor film 103, which becomes theactive layer of the transistor, was created. See FIG. 1A.

Next, gate insulator layer 104 is formed by means of ECR-PECVD, PECVD,or other deposition method. In Example 1, a SiO₂ film was used as thegate insulator layer and was deposited to a thickness of 1200 Å usingPECVD. See FIG. 1B. Immediately prior to setting the substrate in thePECVD reactor, the substrate was soaked for 20 seconds in a 1.67% dilutehydrofluoric acid solution to remove the native oxide layer from thesurface of the semiconductor film. There was an interval ofapproximately 15 minutes from the time the oxide layer was removed untilthe time the substrate was loaded in the loadlock chamber of the PECVDreactor. This time interval should be as short as possible in order topreserve MOS interface cleanliness; an interval of about 30 minutes, atmost, is desirable. In the PECVD method, monosilane (SiH₄) and nitrousoxide (N₂ O) were used as source gases to form the gate insulator layerat a substrate temperature of 300° C. A 900 W rf plasma at 13.56 MHz wasgenerated at a pressure of 1.5 torr. The SiH₄ flow rate was 250 sccm andthe N₂ O flow rate was 7000 sccm. The SiO₂ deposition rate was 48.3 Å/s.Immediately before and after the SiO₂ layer was formed under theseconditions, the silicon layer and deposited oxide layer were exposed toan oxygen plasma to improve the MOS interface and the oxide film. Whilemonosilane and nitrous oxide were used as source gases in Example 1, anorganic silane, such as TEOS (Si--(O--CH₂ --CH₃)₄), and an oxidizinggas, such as oxygen, could also be used. In addition, although ageneral-purpose PECVD reactor was used here, naturally, ECR-PECVD couldalso be used to form the insulator layer. Regardless of the type of CVDreactor or source gases used, it is desirable that the insulator layerformation temperature be 350° C. or less. This is important forpreventing thermal degradation of the MOS interface and gate insulatorlayer. The same thing applies to all processes described below. Allprocess temperatures after gate insulator layer deposition must be keptto 350° C. or less. Controlling the process temperature in this wayenables high-performance thin film semiconductor devices to befabricated easily and reliably.

Next, a thin film, which becomes gate electrode 105, is deposited bysuch means as sputtering, evaporation, or CVD. In Example 1, tantalum(Ta) was selected as the gate electrode material and was deposited to athickness of 5000 Å by means of sputtering. The substrate temperatureduring sputtering was 180° C., and argon (Ar) containing 6.7% nitrogen(N₂) was used as the sputtering gas. The optimum nitrogen concentrationin the argon is from 5.0% to 8.5%. The tantalum film obtained underthese conditions is mostly α-Ta with a resistivity of 40 μΩcm.Therefore, the sheet resistivity of the gate electrode in Example 1 is0.8 μ/square.

Patterning is carried out after the thin film which becomes the gateelectrode is deposited. Then impurity ions 106 such as phosphorous wereimplanted using a bucket-type non-mass-separating ion doping apparatus(ion doping) to form source and drain regions 107 and channel region 108in the intrinsic silicon layer. See FIG. 1C. In Example 1, the objectivewas to fabricate NMOS TFTs, so implantation was carried out to 5×10¹⁵1/cm² using hydrogen-diluted 5% phosphine (PH₃) source gas at a highfrequency power of 38 W and an acceleration voltage of 80 kV. A suitablevalue ranging from about 20 W to 150 W was used for the high frequencypower. During PMOS TFT fabrication, implantation was carried out toabout 5×10¹⁵ 1/cm² using a hydrogen-diluted 5% diborane (B₂ H₆) sourcegas, a high frequency power of between 20 W to 150 W, and anacceleration voltage of 60 kV. When fabricating CMOS TFTs, the NMOS andPMOS are alternately covered with a mask of suitable material, such aspolyimide resin; and ions are implanted into each using the methoddescribed above.

Next, interlevel insulator layer 109 was deposited to 5000 Å. In Example1, the interlevel insulator layer was formed by PECVD using SiO₂. In thePECVD method, the interlevel insulator layer was formed at a substratetemperature of 300° C. using TEOS (Si--(O--CH₂ --CH₃)₄) and oxygen (O₂)as source gases. An 800 W rf plasma at 13.56 MHz was generated at apressure of 8.0 torr. The TEOS flow rate was 200 sccm, and the O₂ flowrate was 8000 sccm. The deposition rate for the SiO₂ film at this timewas 120 Å/s. After ions were implanted and the interlevel insulatorlayer was formed, thermal annealing was performed for 1 hour at 300° C.in an oxygen atmosphere to achieve activation of implanted ions anddensification of the interlevel insulator layer. The desired temperatureof this thermal annealing is between 300° C. and 350° C. Contact holesare opened after thermal annealing is performed, and source and drainelectrodes 110 are formed by sputtering or other means to complete thethin film semiconductor device. See FIG. 1D. Indium tin oxide (ITO) andaluminum (Al) and the like are used for source and drain electrodes. Thetemperature of the substrate during sputtering of these conductors is inthe approximate range of 100° C. to 250° C.

The transistor characteristics of the thin film semiconductor devicesthat were experimentally fabricated in this way were measured. It wasfound that I_(ON) =(23.3+1.73, -1.51)×10⁻⁶ A at a 95% confidence level.Here, the on current, I_(ON), is defined as the source-drain current Idswhen transistors are turned on at source-drain voltage of Vds=4 V andgate voltage of Vgs=10 V. The off current when the transistor was turnedoff at Vds=4 V and Vgs=0 V was I_(OFF) =(1.16+0.38, -0.29)×10⁻¹² A.These measurements were taken at a temperature of 25° C. for transistorshaving channel length L=10 μm and width W=10 μm. The effective electronmobility (J. Levinson et al. J. Appl. Phys. 53, 1193' 82) found from thesaturation current region was μ=50.92±3.26 cm² /v.sec. Conventional lowtemperature process poly-Si TFTs have I_(ON) =(18.7+2.24, -2.09)×10⁻⁶ A,and I_(OFF) =(4.85+3.88, -3.27)×10⁻¹² A. As described, this inventionachieves for the first time, by means of a low temperature process inwhich a maximum processing temperature of 425° C. or less is maintainedfor no more than several hours, extremely good and uniform thin filmsemiconductor devices that have high mobility, low variation, and Idsthat changes seven orders of magnitude or more for a gate voltage changeof 10 V. As described previously, the uniformity of lasercrystallization, whether within a single substrate or from lot to lot,has been a serious problem. This invention, however, greatly reducesvariation of both on current and off current. The improvement overexisting technologies in off current uniformity is particularly marked;and when thin film semiconductor devices fabricated as described by thisinvention are applied to LCDs, a uniform, high-quality picture isobtained over the entire LCD screen. Moreover, improved uniformity meansthat the initial silicon film is stable with respect to variations inthe laser source; thus, this invention also effects conspicuousimprovement with respect to variations among production lots. Asdescribed, this invention achieves extremely reliable crystallization ofsilicon through the use of energy irradiation, such as laserirradiation. Tests performed by the inventor verified that when theinitial silicon layer was formed at low temperature of less than 450° C.and at a silicon layer deposition rate of more than approximately 2Å/min, the silicon layer was stable with respect to variations of thelaser and, moreover, that thin film semiconductor devices having goodtransistor properties are fabricated even when a SiO₂ layer not formedby ECR-PECVD is used as the gate insulator layer. In addition, poly-Silayers obtained by this method are also stable with respect to lightlydoped drain (LDD) structure formation by means of ion doping, as isdescribed later, and are easily activated. This is indirectly related tothe fact that a-Si layers formed under these conditions are perfectlyamorphous without microcrystalline grains, and that the components thatmake up the a-Si layer are made of large regions. Because the a-Si layerdoes not contain microcrystallites, the crystallization that accompaniesenergy irradiation progresses uniformly within the irradiated region. Atthe same time, because the a-Si layer is composed of large regions, thesize of the grains after crystallization is large and high-performanceelectrical characteristics can be obtained. In other words, ideal a-Sifilms can be obtained by optimizing the deposition conditions for theinitial a-Si layer; and uniform, high-quality poly-Si films can beobtained by crystallizing this initial a-Si layer. Amorphous siliconfilms formed using technology of the prior art suffered from theproblems described above, as no heed was paid to the quality of the a-Silayer; for example, deposition temperature in the LPCVD process wasabout 550° C., and substrate temperature in the PECVD method was in theneighborhood of 400° C. One more important point of this invention isthat the process temperature after poly-Si film formation is held to350° C. or less. By controlling the temperature in this way, MOSinterface and insulator layer quality can be stabilized. In this sense,this invention, as shown in FIGS. 1A-1D, is especially useful fortop-gate TFTs. In the case of bottom-gate TFTs, the silicon layer isdeposited after the gate insulator layer has been formed and, moreover,is later subjected to crystallization by laser irradiation or othermeans. Therefore, part of the MOS interface and gate insulator layer is,of necessity, exposed, albeit for a brief time, to a high-temperaturethermal environment of nearly 1000° C. This thermal environment not onlyroughens the MOS interface but also alters the chemical composition andchemical bonds of the insulator layer in the vicinity of the MOSinterface, thus causing transistor characteristics to deteriorate andtriggering the problem of increased non-uniformity.

EXAMPLE 2

Other examples of implementations of this invention will also beexplained using FIGS. 1A-1D.

In Example 2, sheets of non-alkaline glass (OA-2 manufactured by NipponElectric Glass Co., Ltd.) measuring 300 mm×300 mm and crystallized glass(TRC-5 manufactured by Ohara) measuring 300 mm×300 mm were used forsubstrate 101. The strain point of OA-2 is approximately 650° C. TRC-5,on the other hand, is a crystallized glass, so the strain point cannotbe defined. Since absolutely no substrate deformation or warpage can bedetected up to a temperature of about 700° C., however, the strain pointof TRC-5 can, in practice, be said to be above about 700° C. First,silicon oxide film 102, which becomes the underlevel protection layer,was deposited by PECVD onto substrate 101. The silicon oxide film wasdeposited under the same conditions that the gate insulator layer wasdeposited in Example 1. The thickness of the silicon oxide film was 300nm, and the center line mean surface roughness was 0.98 nm. As with thegate insulator layer in Example 1, the underlevel protection layersurface was exposed to an oxygen plasma for 15 seconds both immediatelybefore and immediately after oxide film deposition.

An intrinsic silicon layer, which later becomes the active layer of thethin film semiconductor device, was then deposited to approximately 500Å. Just as in Example 1, the intrinsic silicon layer was deposited bythe high vacuum LPCVD reactor described in section (2-3). The sourcegas, disilane (Si₂ H₆), was introduced at a flow rate of 400 sccm; anddeposition occurred at a temperature of 425° C. and a pressure of 320mtorr. The deposition rate was 1.30 nm/min. Thirty-five OA-2 substratesand 35 TRC-5 substrates were placed in the deposition chamber, which wasmaintained at 250° C. Each OA-2 substrate was paired back-to-back with aTRC-5 substrate. The TRC-5 substrates were placed facedown and the OA-2substrates were placed faceup on top of the TRC-5 substrates. There wasa 10 mm space between substrate pairs. The area of the region in thedeposition chamber over which the semiconductor film was deposited was88262 cm², and the disilane flow rate per unit area was 4.53×10⁻³sccm/cm². After the substrates were placed in the chamber, the chamberwas heated over a period of one hour from the 250° C. insertiontemperature to the 425° C. deposition temperature; and, after thermalequilibrium was achieved at 425° C., the silicon layer was depositedover 40 minutes. The pressure during film deposition was maintained at320 mtorr by the LPCVD reactor's pressure control unit. The thickness ofthe silicon films deposited in this manner was 52.4 nm.

Next, these a-Si films were exposed briefly to optical energy orelectromagnetic energy to melt crystallize the a-Si and transform itinto polysilicon (poly-Si). A xenon chloride (XeCl) excimer laser(wavelength of 308 nm) was also used in Example 2. The substrates weresoaked for 20 seconds in a solution of 1.67% hydrofluoric acidimmediately prior to laser irradiation to remove the native oxide layerfrom the surface of the semiconductor layer. There was a time intervalof approximately 20 minutes after the oxide layer was removed and beforelaser irradiation. After the semiconductor layer was crystallized,poly-Si TFTs were fabricated by the low temperature process usingexactly the same process as described in Example 1.

The transistor characteristics of the thin semiconductor devicesexperimentally fabricated in this way were measured. It was found thaton current was I_(ON) =(41.9+2.60, -2.25)×10⁻⁶ A at a 95% confidencelevel. Off current was I_(OFF) =(6.44+2.11, -1.16)×10⁻¹³ A. Themeasurement conditions here were the same as the conditions inExample 1. Effective electron mobility was μ=90.13±4.61 cm² /v.sec.Extremely good thin film semiconductor devices were fabricated reliablyusing a simple process.

EXAMPLE 3

After forming the poly-Si layer using the method described in detail inExample 1, an SiO₂ layer corresponding to the gate insulator layerdescribed in detail in Example 1 was deposited without patterning thispoly-Si layer, and impurity ions such as PH₃ were implanted in thepoly-Si layer by ion doping, details of which were explained inExample 1. The thicknesses of the poly-Si layer and SiO₂ layer and theconditions under which they were deposited were exactly the same as theywere in Example 1. Impurity ion implantation conditions were also thesame as those described in Example 1 except that the implantation dosewas 3×10¹³ cm⁻². Example 3 corresponds to the formation of the LDDregion in TFTs explained in Example 1. After phosphorous ions wereimplanted, thermal annealing was performed at 300° C. in oxygen for onehour, again just as in Example 1. After that the insulator layer wasstripped off and the sheet resistance of the n-type poly-Si layer thatcontained phosphorous ions was measured. Sheet resistance of a 221mm×221 mm square region excluding the 7 mm periphery of the substratewas (14± 2.6) kΩ/square at a confidence level of 95%. In the prior art,as reported on page 437 of SSDM '93 (solid state Devices and Materials1993), activation was not possible without adding a special process suchas hydrogen implantation. Moreover, the sheet resistance value at thattime was high, 50 kΩ or more, and its variation was 10 kΩ or more. Incontrast, this invention allows a low-resistance LDD region to be simplyformed using ion doping and makes it possible to achieve resistancevariation of no more than one-quarter that of the past.

EXAMPLE 4

In Example 4, the underlevel protection layer and semiconductor layerwere formed sequentially by means of PECVD using 13.56 MHz rf waves.Crystallization was then performed to fabricate the thin filmsemiconductor device.

Substrate 101 was a 360 mm×465 mm×0.7 mm sheet of non-alkaline glass.Prior to placement of the glass substrate in the PECVD reactor, the thinfilm that formed in the deposition chamber during deposition of the thinfilm on the previous substrate is removed from the deposition chamber.In other words, the deposition chamber is cleaned for 15 seconds. Thecleaning conditions were rf power of 1600 W (0.8 W/cm²) , electrodeseparation distance of 40 mm, NF₃ flow rate of 3200 sccm, argon flowrate of 800 sccm, and pressure of 1.0 torr. Next, after a vacuum ispulled for 15 seconds, a silicon nitride layer, which serves as thepassivation layer, is deposited for 15 seconds in the depositionchamber. The deposition conditions were rf power of 300 W (0.15 W/cm²),electrode separation distance of 40 mm, pressure of 1.2 torr, nitrogenflow rate of 3500 sccm, ammonia flow rate of 500 sccm, and monosilaneflow rate of 100 sccm. After a vacuum is pulled for 15 seconds, thesubstrate is placed in the deposition chamber. It takes approximately 10seconds for the substrates that are set up in the loadlock chamber to bepositioned in the deposition chamber. A stabilization period of 30seconds is allowed before the next underlevel protection layer isdeposited. All process parameters for the stabilization period areidentical to the deposition conditions for the underlevel protectionlayer, except that plasma is not generated. The lower plate electrodetemperature, from the underlevel protection layer to the depositedsemiconductor film, is 360° C.; and the substrate surface temperature isapproximately 340° C. After the stabilization period expires, theunderlevel protection layer is deposited. The underlevel protectionlayer consists of a deposited layer of silicon nitride and a layer ofsilicon oxide. First, the silicon nitride layer is deposited over 30seconds at rf power of 800 W, electrode separation distance of 25 mm,pressure of 1.2 torr, nitrogen flow rate of 3500 sccm, ammonia flow rateof 500 sccm, and monosilane flow rate of 100 sccm. The silicon oxidelayer is then deposited for 30 seconds at rf power of 900 W, electrodeseparate distance of 25 mm, pressure of 1.5 torr, monosilane flow rateof 250 sccm, and N₂ O flow rate of 7000 sccm. The nitride and oxidelayers are each approximately 150 nm thick, forming an underlevelprotection layer about 300 nm thick. After formation, the oxide layer isexposed to an oxygen plasma for 20 seconds. Oxygen plasma was irradiatedat rf wave power of 900 W (0.45 W/cm²) , electrode separation distanceof 12 mm, pressure of 0.65 torr, and oxygen flow rate of 3000 sccm.After a vacuum is pulled for 15 seconds, the oxide layer is exposed tohydrogen plasma for 20 seconds. The hydrogen plasma conditions were rfpower of 100 W (0.05 W/cm²), electrode separation distance of 25 mm,pressure of 0.5 torr, and hydrogen flow rate of 1400 sccm. Uponcompletion of hydrogen plasma irradiation, the semiconductor layer isdeposited over 60 seconds. The deposition conditions were rf power of600 W (0.3 W/cm²), electrode separation distance of 35 mm, pressure of1.5 torr, argon flow rate of 14 SLM, and monosilane flow rate of 200sccm. This deposits an amorphous silicon film approximately 50 nm thick.After deposition of the semiconductor layer a vacuum is pulled for 15seconds, and the amorphous silicon film is exposed to hydrogen plasmafor 20 seconds. The hydrogen plasma is generated under the sameconditions as the hydrogen plasma that was generated prior tosemiconductor layer deposition. Next, after a vacuum is pulled for 15seconds, the amorphous silicon film is exposed to oxygen plasma for 20seconds. The conditions under which oxygen plasma is generated are thesame as those under which the oxygen plasma was generated afterunderlevel protection layer formation except for the fact that thedistance between electrodes is 45 mm. Finally, after a vacuum is pulledfor 15 seconds, the substrates are removed from the deposition chamberin about 10 seconds. With this process, tact time is 6 minutes and 10seconds, making it possible to sequentially deposit the underlevelprotection layer and the semiconductor layer. After this, thin filmsemiconductor devices were fabricated using the exact same process aswas described in Example 2.

The transistor characteristics of thin film semiconductors that wereexperimentally fabricated in this way were measured. It was found thaton current was I_(ON) =(19.6+1.54, -1.49)×10⁻⁶ A at a 95% confidencelevel, and that off current was I_(OFF) =7.23+2.76, -2.72)×10⁻¹³ A.Effective electron mobility was μ=36.83±2.35 cm² /v.sec. The measurementconditions correspond to those described in Example 1.

EXAMPLE 5

Next, a low temperature process (350° C. or less) for depositing, usingthe PECVD reactor that was explained in section (2-11), crystallinesemiconductor films that do not require crystallization by laserirradiation or other irradiation means; the method of fabricating thinfilm semiconductor devices using this method; and the characteristics ofthese films will be described in detail. The substrates are prepared bythe method described in section (2-1). Although the semiconductor layersand source gases described in section (2-2) are all applicable, siliconfilm is discussed here as an example and monosilane (SiH₄) is used asthe source gas.

In Example 5, substrate 101 was a 360 mm×465 mm×1.1 mm sheet ofnon-alkaline glass (OA-2, manufactured by Nippon Electric Glass Co.,Ltd.), and the SiO₂ layer of the underlevel protection layer wasdeposited to a thickness of 2000 Å by means of APCVD using SiH₄ and O₂as source gases. The substrate temperature was 300° C.

Then, an approximately 750 Å intrinsic silicon layer, which becomes theactive layer of the thin film semiconductor device, was deposited. Theintrinsic silicon layer was deposited by means of a VHF-PECVD reactor,described previously in section (2-11), using a 50 sccm flow rate ofmonosilane (SiH₄) as the source gas and a 4800 sccm flow rate of argon(Ar), one of the noble gas elements, as a dilution gas. Duringdeposition of the intrinsic silicon layer, the VHF wave power was 715 W,the pressure in the reactor chamber was 0.8 torr, the distance betweenparallel plate electrodes was 35.0 mm, the lower plate electrodetemperature was 400° C., and the substrate surface temperature was 340°C. The semiconductor layer obtained in this way is a silicon layer ofhigh purity and is polycrystalline in the state immediately afterdeposition ("as-deposited"). The degree of crystallinity was measuredusing multiple wavelength spectroscopic ellipsometry and was found to be78%. Usually, if the degree of crystallinity found by means ofspectroscopic ellipsometry is less than 30%, the silicon layer isconsidered to be amorphous; if it is 70% or more, the layer isconsidered to be polycrystalline; and if it is between 30% and 70%, itis considered to be mixed. Hence, the film that was obtained was clearlypolycrystalline in the as-deposited state. In fact, a sharp Raman shiftwas detected by means of Raman spectroscopy in the wave number region inthe vicinity of 520 cm⁻¹, which indicates a crystalline state; inaddition, it was observed by means of X-ray diffraction that thecrystals have a relatively strong preferred orientation in the {220}direction.

Next, this silicon layer was patterned and channel area semiconductorlayer 103, which becomes the active layer of the transistor, was formed,see FIG. 1A. Using exactly the same processes as those that were used tofabricate the thin film semiconductor device that was explained indetail in Example 1, the gate insulator layer was formed, see FIG. 1B,the gate electrode was formed, the source and drain regions and channelwere formed by ion implantation, see FIG. 1C, the interlevel insulatorlayer was formed, implanted ions were activated and the interlevelinsulation layer was densified by thermal annealing, contact holes wereopened, source and drain electrodes were formed, and the thin filmsemiconductor device was then completed, see FIG. 1D. In Example 5,therefore, the maximum processing temperature after the first process,that of semiconductor layer formation, was 300° C. The temperature ofthe process for forming the gate insulator layer and the temperature ofthe thermal annealing process for implanted ion activation andinterlevel insulator layer densification must not exceed a maximumtemperature of 350° C. In other words, as detailed in section (2-10), touniformly and reliably fabricate excellent thin film semiconductordevices over large areas, the maximum process temperature after thefirst process, that of semiconductor layer formation, must not exceed350° C.

The transistor characteristics of the thin film semiconductor devicesthat were experimentally fabricated in this way were measured. It wasfound that I_(ON) =(1.22+0.11, -0.10)×10⁻⁶ A at a 95% confidence level.Here, the on current, I_(ON), is defined as the source-drain current Idswhen transistors are turned on at source-drain voltage of Vds=4 V andgate voltage of Vgs=10 V. The off current when the transistor was turnedoff at Vds=4 V and Vgs=0 V was I_(OFF) =(1.18+0.35, -0.30)×10⁻¹³ A. Themeasurements were taken at a temperature of 25° C. for transistorshaving channel length L=10 μm and width W=10 μm. The effective electronmobility (J. Levinson et al. J. Appl. Phys. 53, 1193'82) found from thesaturation current region was μ=3.41±0.22 cm² /v. sec.

The maximum process temperature reached in Example 5 was the 400° C.lower plate electrode temperature during deposition of the semiconductorlayer by means of a VHF-PECVD reactor; the substrate surface temperatureat that time was 340° C. As shown by this example, poly-Si TFTs, whichare a kind of crystalline thin film semiconductor device, weresuccessfully fabricated at extremely low process temperature using asimple manufacturing method that does not require crystallization bylaser irradiation or other means. While values for on current andmobility are far from those in Example 1, in which laser irradiation wasemployed, they are from 4 to nearly 10 times higher than the values fora-Si TFTs fabricated by conventional methods with a maximum processingtemperature of 400° C. Additionally, source and drain regions in Example5 were formed by means of ion implantation with the gate electrode usedas a mask. Moreover, because implanted ions were activated at lowtemperatures of from 300° C. to 350° C., implanted ions from the sourceand drain regions essentially do not diffuse at all into the channelregion. Therefore, the overlapping of gate electrodes and source anddrain regions is determined by horizontal projection deviation duringion implantation, and the deviation value is not more than severalhundred Å. In other words, the edges of the gate electrode and the edgesof the source and drain matched extremely closely in a so-calledself-aligned structure. For that reason, the parasitic capacitancebetween source and gate and between drain and gate is extremely small incomparison with that of a-Si TFTs. Due to these two facts, when the thinfilm semiconductor devices of this invention are used as pixel switchingelements for an active-matrix liquid crystal display device (LCD),high-definition LCDs (LCDs having a large number of picture elements),bright LCDs (LCDs having a high aperture ratio in which storagecapacitors have been reduced or eliminated), and highly-integrated LCDs(LCDs having a large number of picture elements per unit area), all ofwhich were heretofore impossible using a-Si TFTs of the prior art, caneasily be achieved.

EXAMPLE 6

Next, a low temperature process, having a maximum temperature of about350° C. in which a microwave PECVD reactor is used to depositcrystalline semiconductor films that do not require crystallization bymeans of laser irradiation or other means, a method for fabricating thinfilm semiconductor devices using that method, and the characteristics ofthese thin film semiconductor devices will be described in detail. Thesubstrate is prepared using the method described in section (2-1). Thesemiconductor film and source gases described in section (2-2) can allbe applied, but here, for illustrative purposes, silicon film is usedand monosilane (SiH₄) is used as the source gas.

In Example 6, a 300 mm×300 mm×1.1 mm sheet of non-alkaline glass (OA-2,manufactured by Nippon Electric Glass Co., Ltd.) was used for substrate101, and the underlevel protection layer and semiconductor layer weredeposited sequentially at a substrate temperature of 100° C. by means ofECR-PECVD reactor, a type of microwave PECVD reactor. The microwavesused were 2.45 GHz. The silicon oxide layer, which is the underlevelprotection layer, was deposited to 200 nm using SiH₄ and O₂ as sourcegases. The underlevel protection layer was deposited using an oxygenflow rate of 100 sccm, silane flow rate of 60 sccm, microwave power of2250 w, reactor chamber pressure of 2.35 mtorr, and a deposition rate of8.0 nm/s. After formation of the silicon oxide layer, the flow of silaneto the deposition chamber was shut off and the silicon oxide layer wasexposed to an oxygen plasma for 10 seconds. The pressure during oxygenplasma irradiation was 1.85 mtorr. Then, after a vacuum was pulled for10 seconds, the underlevel protection layer was exposed to a hydrogenplasma using a hydrogen flow rate of 100 sccm, microwave power of 2000W, and reaction chamber pressure of 1.97 mtorr. Next, without breakingthe vacuum, an intrinsic silicon layer, which becomes the active layerof the thin film semiconductor device, was successively deposited toabout 75 nm. The intrinsic silicon layer was deposited by introducingmonosilane (SiH₄), the source gas, at the rate of 25 sccm and argon(Ar), an element in the noble gas family, as a dilution gas at the rateof 825 sccm. The film deposition conditions were microwave power of 2250W, reaction chamber pressure of 13.0 mtorr, and deposition rate of 2.5nm/s. After deposition, the semiconductor layer was again exposed insuccession to a hydrogen plasma and an oxygen plasma for the purpose ofprotecting the surface of the semiconductor layer and terminatingdangling bonds in the semiconductor layer. The conditions under whichthe hydrogen plasma and oxygen plasma were generated were identical tothose used for the underlevel protection layer. The semiconductor filmobtained in this way is a high purity silicon layer and ispolycrystalline in the state immediately after deposition (theas-deposited state). The degree of crystallinity was measured usingmultiple wavelength spectroscopic ellipsometry and was found to be 85%.

Next, this silicon layer was patterned and channel region semiconductorfilm 103, which becomes the active layer of the transistor, was formed.See FIG. 1A. Using exactly the same processes as those that were used tofabricate the thin film semiconductor device that was explained indetail in Example 1, the gate insulator layer was formed, see FIG. 1B,the gate electrode was formed, the source and drain regions and channelwere formed by ion implantation, see FIG. 1C, the interlevel insulatorlayer was formed, implanted ions were activated and the interlevelinsulator layer was densified by thermal annealing, contact holes wereopened, source and drain electrodes were formed, and the thin filmsemiconductor device was then completed, see FIG. 1D. In Example 6,therefore, the maximum processing temperature throughout all processingsteps was 300° C.

The transistor characteristics of the thin film semiconductor devicesthat were experimentally fabricated in this way were measured. It wasfound, with a 95% confidence level, that on current was I_(ON)=(1.71+0.13, -0.12)× 10⁻⁶ A and off current was I_(OFF) =(1.07+0.33,-0.28)×10⁻¹³ A. Effective electron mobility was μ=4.68±0.20 cm² /v.sec.Measurement conditions conform to those in Example 1. Using thisinvention, poly-Si TFTs can be fabricated by a process in which allprocess temperatures are 300° C. or less and without even introducing aspecial crystallization step.

EXAMPLE 7

In this example, a semiconductor film obtained by VHS-PECVD was exposedto laser irradiation to achieve melt crystallization and create a thinfilm semiconductor device. The fabrication process was the same as thatdescribed in Example 5 except that the laser irradiation process wasadded immediately after the semiconductor film was deposited. The laserirradiation method used was the same as that described in Example 1,with the energy density of the first laser exposure changed to 130mJ/cm², and the energy density of the second laser exposure changed to240 mJ/cm².

The transistor characteristics of the thin film semiconductor devicesthat were experimentally fabricated in this way were measured. It wasfound, with a 95% confidence level, that on current was I_(ON)=(22.4+1.70, -1.55)×10⁻⁶ A and off current was I_(OFF) =(1.27+0.30,-0.26)×10⁻¹² A. Effective electron mobility was μ=47.95±3.13 cm² /v.sec.Measurement conditions conform to those in Example 1.

EXAMPLE 8

In this example a semiconductor film obtained by microwave-PECVD wasexposed to laser irradiation to achieve melt crystallization and createa thin film semiconductor device. The fabrication process was the sameas that described in Example 6 except that a laser irradiation processwas added immediately after the semiconductor film was deposited. Thelaser irradiation method used was the same as that described in Example1, with the energy density of the first laser exposure changed to 150mJ/cm² and the energy density of the second laser irradiation exposurechanged to 270 mJ/cm².

The transistor characteristics of the thin film semiconductor devicesthat were experimentally fabricated in this way were measured. It wasfound, with a 95% confidence level, that on current was I_(ON)=(39.8+2.45, -1.57)×10⁻⁶ A and off current was I_(OFF) =(5.80+2.09,-1.26)×10⁻¹³ A. Effective electron mobility was μ=85.63±4.38 cm² /v.sec.Measurement conditions conform to those in Example 1.

EXAMPLE 9

Active matrix substrates using each of the thin film semiconductordevices obtained by the methods described in the above examples as pixelTFTs and driver circuit TFTs were manufactured. Liquid crystal panelswere produced using some of these active matrix substrates. Liquidcrystal display device modules were manufactured by equipping theseliquid crystal panels with external peripheral drivers and a backlightunit. The performance of the TFTs themselves was high-quality, and sincethe manufacturing process is also reliable, it was possible tomanufacture liquid crystal display devices having high display qualityat low cost. In addition, the performance of TFTs was extremely high,and since the necessary driver circuits can be formed on the activematrix substrate (integrated drivers), it was possible to simplify thepackaging configuration with the outside peripheral driver circuits andachieve a compact, lightweight liquid crystal display device.

These types of liquid crystal display devices were installed in the caseof a full-color notebook PC, thus achieving at low cost the manufactureof a compact, lightweight full-color notebook PC having good displayquality.

Possible Industrial Applications

As stated above, the method of fabricating thin film semiconductordevices described by this invention enables the manufacture of highperformance thin film semiconductor devices using a low temperatureprocess in which inexpensive glass substrates can be used. Therefore,applying this invention to the manufacture of active matrix liquidcrystal display devices permits large-size, high-quality liquid crystaldisplay devices to be manufactured easily and reliably. Moreover, whenthis invention is applied to the manufacture of other electroniccircuits, high-quality electronic circuits can also be manufacturedeasily and reliably. Additionally, since the thin film semiconductordevice of this invention is both low-cost and high-performance, it isoptimum for active matrix substrates for active matrix liquid crystaldisplays. It is especially well-suited for integrated driver activematrix substrates, which require high performance.

Additionally, since the liquid crystal displays of this invention arelow-cost and high-performance, they are optimum for full-color notebookPCs and all types of displays.

Additionally, since the electronic circuits of this invention arelow-cost and high-performance, they will likely find wide acceptance.

I claim:
 1. A fabrication process for fabricating a thin filmsemiconductor device using a low pressure chemical vapor depositionreactor, comprising:forming an underlevel protection layer comprising aninsulating material formed on at least a portion of a substrate; andforming a silicon-containing semiconductor film on said underlevelprotection layer, the silicon-containing semiconductor film being anactive layer of a transistor, wherein the silicon-containingsemiconductor film is formed with a low pressure chemical vapordeposition method using a higher silane as a source gas, the highersilane being Si_(n) H_(2n+2), where n is an integer greater than orequal to 2, wherein the higher silane has a flow rate per unit area R,with R≧1.13×10⁻³ sccm/cm² when R=Q/A, wherein A (cm²): a total surfacearea inside the low pressure chemical vapor deposition reactor which canbe covered with the silicon-containing semiconductor film, and Q (sccm):flow rate of the higher silane.
 2. A fabrication process as described inclaim 1, wherein the silicon-containing semiconductor film is formedwith R≧2.27×10⁻³ sccm/cm².
 3. A fabrication process for fabricating athin film semiconductor device having a semiconductor film formed on asurface of a glass substrate, said semiconductor film being an activelayer of a transistor, the process comprising:placing a plurality ofsubstrate pairs in a hot wall, vertical low pressure chemical vapordeposition reactor, the substrate pairs being glass substrates and eachone of the substrate pairs having a front side and a back side, a firstone of the substrate pairs having a strain point higher than a strainpoint of a second one of the substrate pairs, the substrate pairs beingplaced in the vertical low pressure chemical vapor deposition reactorhaving the back sides of the first and second ones of the substratepairs against each other, the first one of the substrate pairs beingbelow the second one of the substrate pairs, and the first and secondones of the substrates pairs being approximately parallel to each other;and forming the semiconductor film on the front sides of the first andsecond ones of the substrate pairs.
 4. A fabrication process forfabricating a thin film semiconductor device having an underlevelprotection layer formed on a portion of a substrate and a semiconductorfilm formed on said underlevel protection layer using a plasma enhancedchemical vapor deposition reactor, the underlevel protection layercomprising an insulating material and the semiconductor film being anactive layer of a transistor, the process comprising:exposing theunderlevel protection layer to an oxygen plasma; and then forming thesemiconductor film on top of said underlevel protection layer withoutbreaking a vacuum of the plasma enhanced chemical vapor depositionreactor.
 5. A fabrication process as described in claim 4, wherein thevacuum is engaged in the plasma enhanced chemical vapor depositionreactor between the exposing step and the forming step.
 6. A fabricationprocess for fabricating a thin film semiconductor device having anunderlevel protection layer formed on at least a portion of a substrateand a semiconductor film formed on said underlevel protection layerusing a plasma enhanced chemical vapor deposition reactor, theunderlevel protection layer comprising an insulating material and thesemiconductor film being an active layer of a transistor, the processcomprising:exposing the underlevel protection layer to a hydrogenplasma; and then forming the semiconductor film on top of saidunderlevel protection layer without breaking a vacuum of the plasmaenhanced chemical vapor deposition reactor.
 7. A fabrication process forfabricating a thin film semiconductor device having an underlevelprotection layer formed on at least a portion of a substrate and asemiconductor film formed on said underlevel protection layer using aplasma enhanced chemical vapor deposition reactor, the underlevelprotection layer comprising an insulating material and the semiconductorfilm being an active layer of a transistor, the processcomprising:exposing the underlevel protection layer to an oxygen plasma;then exposing the underlevel protection layer to a hydrogen plasmawithout breaking a vacuum of the plasma enhanced chemical vapordeposition reactor; and then forming the semiconductor film on top ofsaid underlevel protection layer.
 8. A fabrication process as describedin claim 7, wherein the vacuum is engaged in the plasma enhancedchemical vapor deposition reactor between the exposing the underlevelprotection layer to the oxygen plasma step and the exposing theunderlevel protection layer to the hydrogen plasma step.
 9. Afabrication process for fabricating a thin film semiconductor devicehaving an underlevel protection layer formed on at least a portion of asubstrate and a semiconductor film formed on said underlevel protectionlayer using a plasma enhanced chemical vapor deposition reactor, theunderlevel protection layer comprising an insulating material and thesemiconductor film being an active layer of a transistor, the processcomprising:depositing the semiconductor film with a deposition rate ofapproximately 0.1 nm/s or more to form a mixed crystallinitysemiconductor film; and then melt crystallizing said semiconductor film.10. A fabrication process as described in claim 9, wherein thedeposition rate is approximately 3.7 nm/s or more to form themixed-crystallinity semiconductor film.
 11. A fabrication process forfabricating a thin film semiconductor device having an underlevelprotection layer formed on at least a portion of a substrate and asemiconductor film formed on said underlevel protection layer using aplasma enhanced chemical vapor deposition reactor, the underlevelprotection layer comprising an insulating material and the semiconductorfilm being an active layer of a transistor, the processcomprising:forming a mixed-crystallinity semiconductor film, whereinchemical species containing constitutive elements of said semiconductorfilm and inert gases are used as source gases with a ratio of a flowrate of a gas containing the constitutive elements of the semiconductorfilm to a flow rate of the inert gases being less than about 1/33; andmelt crystallizing said mixed-crystallinity semiconductor film.
 12. Afabrication process as described in claim 11, wherein the flow ratio isbetween about 1/124 and 1/40.67.